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add tests for not(or(not(X),not(Y))) -> and(X, Y)
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‎llvm/test/CodeGen/LoongArch/lasx/and-not-combine.ll‎

Lines changed: 106 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -324,3 +324,109 @@ define void @and_not_combine_splatimm_v4i64(ptr %res, ptr %a0) nounwind {
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store <4 x i64> %xor, ptr %res
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ret void
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}
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define void @and_or_not_combine_v32i8(ptr %pa, ptr %pb, ptr %pv, ptr %dst) nounwind {
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; CHECK-LABEL: and_or_not_combine_v32i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: xvld $xr1, $a2, 0
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; CHECK-NEXT: xvld $xr2, $a1, 0
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; CHECK-NEXT: xvseq.b $xr0, $xr1, $xr0
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; CHECK-NEXT: xvxori.b $xr0, $xr0, 255
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; CHECK-NEXT: xvseq.b $xr1, $xr1, $xr2
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; CHECK-NEXT: xvorn.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvandi.b $xr0, $xr0, 4
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; CHECK-NEXT: xvst $xr0, $a3, 0
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; CHECK-NEXT: ret
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%a = load <32 x i8>, ptr %pa
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%b = load <32 x i8>, ptr %pb
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%v = load <32 x i8>, ptr %pv
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%ca = icmp ne <32 x i8> %v, %a
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%cb = icmp ne <32 x i8> %v, %b
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%or = or <32 x i1> %ca, %cb
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%ext = sext <32 x i1> %or to <32 x i8>
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%and = and <32 x i8> %ext, splat (i8 4)
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store <32 x i8> %and, ptr %dst
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ret void
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}
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define void @and_or_not_combine_v16i16(ptr %pa, ptr %pb, ptr %pv, ptr %dst) nounwind {
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; CHECK-LABEL: and_or_not_combine_v16i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: xvld $xr1, $a2, 0
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; CHECK-NEXT: xvld $xr2, $a1, 0
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; CHECK-NEXT: xvseq.h $xr0, $xr1, $xr0
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; CHECK-NEXT: xvrepli.b $xr3, -1
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; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr3
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; CHECK-NEXT: xvseq.h $xr1, $xr1, $xr2
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; CHECK-NEXT: xvorn.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvrepli.h $xr1, 4
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvst $xr0, $a3, 0
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; CHECK-NEXT: ret
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%a = load <16 x i16>, ptr %pa
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%b = load <16 x i16>, ptr %pb
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%v = load <16 x i16>, ptr %pv
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%ca = icmp ne <16 x i16> %v, %a
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%cb = icmp ne <16 x i16> %v, %b
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%or = or <16 x i1> %ca, %cb
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%ext = sext <16 x i1> %or to <16 x i16>
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%and = and <16 x i16> %ext, splat (i16 4)
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store <16 x i16> %and, ptr %dst
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ret void
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}
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define void @and_or_not_combine_v8i32(ptr %pa, ptr %pb, ptr %pv, ptr %dst) nounwind {
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; CHECK-LABEL: and_or_not_combine_v8i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: xvld $xr1, $a2, 0
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; CHECK-NEXT: xvld $xr2, $a1, 0
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; CHECK-NEXT: xvseq.w $xr0, $xr1, $xr0
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; CHECK-NEXT: xvrepli.b $xr3, -1
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; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr3
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; CHECK-NEXT: xvseq.w $xr1, $xr1, $xr2
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; CHECK-NEXT: xvorn.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvrepli.w $xr1, 4
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvst $xr0, $a3, 0
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; CHECK-NEXT: ret
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%a = load <8 x i32>, ptr %pa
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%b = load <8 x i32>, ptr %pb
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%v = load <8 x i32>, ptr %pv
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%ca = icmp ne <8 x i32> %v, %a
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%cb = icmp ne <8 x i32> %v, %b
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%or = or <8 x i1> %ca, %cb
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%ext = sext <8 x i1> %or to <8 x i32>
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%and = and <8 x i32> %ext, splat (i32 4)
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store <8 x i32> %and, ptr %dst
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ret void
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}
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define void @and_or_not_combine_v4i64(ptr %pa, ptr %pb, ptr %pv, ptr %dst) nounwind {
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; CHECK-LABEL: and_or_not_combine_v4i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvld $xr0, $a0, 0
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; CHECK-NEXT: xvld $xr1, $a2, 0
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; CHECK-NEXT: xvld $xr2, $a1, 0
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; CHECK-NEXT: xvseq.d $xr0, $xr1, $xr0
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; CHECK-NEXT: xvrepli.b $xr3, -1
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; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr3
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; CHECK-NEXT: xvseq.d $xr1, $xr1, $xr2
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; CHECK-NEXT: xvorn.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvrepli.d $xr1, 4
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; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
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; CHECK-NEXT: xvst $xr0, $a3, 0
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; CHECK-NEXT: ret
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%a = load <4 x i64>, ptr %pa
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%b = load <4 x i64>, ptr %pb
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%v = load <4 x i64>, ptr %pv
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%ca = icmp ne <4 x i64> %v, %a
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%cb = icmp ne <4 x i64> %v, %b
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%or = or <4 x i1> %ca, %cb
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%ext = sext <4 x i1> %or to <4 x i64>
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%and = and <4 x i64> %ext, splat (i64 4)
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store <4 x i64> %and, ptr %dst
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ret void
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}

‎llvm/test/CodeGen/LoongArch/lsx/and-not-combine.ll‎

Lines changed: 106 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -324,3 +324,109 @@ define void @and_not_combine_splatimm_v2i64(ptr %res, ptr %a0) nounwind {
324324
store <2 x i64> %xor, ptr %res
325325
ret void
326326
}
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define void @and_or_not_combine_v16i8(ptr %pa, ptr %pb, ptr %pv, ptr %dst) nounwind {
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; CHECK-LABEL: and_or_not_combine_v16i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vld $vr0, $a0, 0
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; CHECK-NEXT: vld $vr1, $a2, 0
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; CHECK-NEXT: vld $vr2, $a1, 0
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; CHECK-NEXT: vseq.b $vr0, $vr1, $vr0
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; CHECK-NEXT: vxori.b $vr0, $vr0, 255
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; CHECK-NEXT: vseq.b $vr1, $vr1, $vr2
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; CHECK-NEXT: vorn.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vandi.b $vr0, $vr0, 4
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; CHECK-NEXT: vst $vr0, $a3, 0
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; CHECK-NEXT: ret
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%a = load <16 x i8>, ptr %pa
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%b = load <16 x i8>, ptr %pb
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%v = load <16 x i8>, ptr %pv
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%ca = icmp ne <16 x i8> %v, %a
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%cb = icmp ne <16 x i8> %v, %b
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%or = or <16 x i1> %ca, %cb
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%ext = sext <16 x i1> %or to <16 x i8>
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%and = and <16 x i8> %ext, splat (i8 4)
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store <16 x i8> %and, ptr %dst
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ret void
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}
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define void @and_or_not_combine_v8i16(ptr %pa, ptr %pb, ptr %pv, ptr %dst) nounwind {
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; CHECK-LABEL: and_or_not_combine_v8i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vld $vr0, $a0, 0
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; CHECK-NEXT: vld $vr1, $a2, 0
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; CHECK-NEXT: vld $vr2, $a1, 0
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; CHECK-NEXT: vseq.h $vr0, $vr1, $vr0
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; CHECK-NEXT: vrepli.b $vr3, -1
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; CHECK-NEXT: vxor.v $vr0, $vr0, $vr3
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; CHECK-NEXT: vseq.h $vr1, $vr1, $vr2
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; CHECK-NEXT: vorn.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vrepli.h $vr1, 4
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; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a3, 0
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; CHECK-NEXT: ret
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%a = load <8 x i16>, ptr %pa
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%b = load <8 x i16>, ptr %pb
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%v = load <8 x i16>, ptr %pv
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%ca = icmp ne <8 x i16> %v, %a
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%cb = icmp ne <8 x i16> %v, %b
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%or = or <8 x i1> %ca, %cb
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%ext = sext <8 x i1> %or to <8 x i16>
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%and = and <8 x i16> %ext, splat (i16 4)
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store <8 x i16> %and, ptr %dst
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ret void
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}
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define void @and_or_not_combine_v4i32(ptr %pa, ptr %pb, ptr %pv, ptr %dst) nounwind {
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; CHECK-LABEL: and_or_not_combine_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vld $vr0, $a0, 0
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; CHECK-NEXT: vld $vr1, $a2, 0
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; CHECK-NEXT: vld $vr2, $a1, 0
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; CHECK-NEXT: vseq.w $vr0, $vr1, $vr0
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; CHECK-NEXT: vrepli.b $vr3, -1
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; CHECK-NEXT: vxor.v $vr0, $vr0, $vr3
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; CHECK-NEXT: vseq.w $vr1, $vr1, $vr2
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; CHECK-NEXT: vorn.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vrepli.w $vr1, 4
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; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a3, 0
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; CHECK-NEXT: ret
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%a = load <4 x i32>, ptr %pa
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%b = load <4 x i32>, ptr %pb
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%v = load <4 x i32>, ptr %pv
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%ca = icmp ne <4 x i32> %v, %a
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%cb = icmp ne <4 x i32> %v, %b
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%or = or <4 x i1> %ca, %cb
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%ext = sext <4 x i1> %or to <4 x i32>
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%and = and <4 x i32> %ext, splat (i32 4)
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store <4 x i32> %and, ptr %dst
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ret void
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}
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define void @and_or_not_combine_v2i64(ptr %pa, ptr %pb, ptr %pv, ptr %dst) nounwind {
408+
; CHECK-LABEL: and_or_not_combine_v2i64:
409+
; CHECK: # %bb.0:
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; CHECK-NEXT: vld $vr0, $a0, 0
411+
; CHECK-NEXT: vld $vr1, $a2, 0
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; CHECK-NEXT: vld $vr2, $a1, 0
413+
; CHECK-NEXT: vseq.d $vr0, $vr1, $vr0
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; CHECK-NEXT: vrepli.b $vr3, -1
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; CHECK-NEXT: vxor.v $vr0, $vr0, $vr3
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; CHECK-NEXT: vseq.d $vr1, $vr1, $vr2
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; CHECK-NEXT: vorn.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vrepli.d $vr1, 4
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; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a3, 0
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; CHECK-NEXT: ret
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%a = load <2 x i64>, ptr %pa
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%b = load <2 x i64>, ptr %pb
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%v = load <2 x i64>, ptr %pv
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%ca = icmp ne <2 x i64> %v, %a
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%cb = icmp ne <2 x i64> %v, %b
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%or = or <2 x i1> %ca, %cb
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%ext = sext <2 x i1> %or to <2 x i64>
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%and = and <2 x i64> %ext, splat (i64 4)
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store <2 x i64> %and, ptr %dst
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ret void
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}

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