fixup! Address CR comments and remove optional register code (will push this later)

Author: jthackray

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

@@ -3908,8 +3908,6 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
   StringRef Op = Tok.getString();
   SMLoc S = Tok.getLoc();
   bool ExpectRegister = true;
-  bool OptionalRegister = false;
-  bool hasAll = getSTI().hasFeature(AArch64::FeatureAll);
 
   if (Mnemonic == "ic") {
     const AArch64IC::IC *IC = AArch64IC::lookupICByName(Op);
@@ -3958,6 +3956,7 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
     if (Op.lower() != "rctx")
       return TokError("invalid operand for prediction restriction instruction");
 
+    bool hasAll = getSTI().hasFeature(AArch64::FeatureAll);
     bool hasPredres = hasAll || getSTI().hasFeature(AArch64::FeaturePredRes);
     bool hasSpecres2 = hasAll || getSTI().hasFeature(AArch64::FeatureSPECRES2);
 
@@ -3990,12 +3989,10 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
     HasRegister = true;
   }
 
-  if (!OptionalRegister) {
-    if (ExpectRegister && !HasRegister)
-      return TokError("specified " + Mnemonic + " op requires a register");
-    else if (!ExpectRegister && HasRegister)
-      return TokError("specified " + Mnemonic + " op does not use a register");
-  }
+  if (ExpectRegister && !HasRegister)
+    return TokError("specified " + Mnemonic + " op requires a register");
+  else if (!ExpectRegister && HasRegister)
+    return TokError("specified " + Mnemonic + " op does not use a register");
 
   if (parseToken(AsmToken::EndOfStatement, "unexpected token in argument list"))
     return true;

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

@@ -917,7 +917,6 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
   Encoding |= Op1Val << 11;
 
   bool NeedsReg;
-  bool OptionalReg = false;
   std::string Ins;
   std::string Name;
 
@@ -1021,20 +1020,18 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
   StringRef Reg = getRegisterName(MI->getOperand(4).getReg());
   bool NotXZR = Reg != "xzr";
 
-  // If a mandatory or optional register is not specified in the TableGen
+  // If a mandatory is not specified in the TableGen
   // (i.e. no register operand should be present), and the register value
   // is not xzr/x31, then disassemble to a SYS alias instead.
-  if (NotXZR && !NeedsReg && !OptionalReg)
+  if (NotXZR && !NeedsReg)
     return false;
 
   std::string Str = Ins + Name;
   llvm::transform(Str, Str.begin(), ::tolower);
 
   O << '\t' << Str;
 
-  // For optional registers, don't print the value if it's xzr/x31
-  // since this defaults to xzr/x31 if register is not specified.
-  if (NeedsReg || (OptionalReg && NotXZR)) {
+  if (NeedsReg) {
     O << ", " << Reg;
   }
 

llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h

@@ -409,16 +409,6 @@ struct SysAliasReg : SysAlias {
       : SysAlias(N, E, F), NeedsReg(R) {}
 };
 
-struct SysAliasOptionalReg : SysAlias {
-  bool NeedsReg;
-  bool OptionalReg;
-  constexpr SysAliasOptionalReg(const char *N, uint16_t E, bool R, bool O)
-      : SysAlias(N, E), NeedsReg(R), OptionalReg(O) {}
-  constexpr SysAliasOptionalReg(const char *N, uint16_t E, bool R, bool O,
-                                FeatureBitset F)
-      : SysAlias(N, E, F), NeedsReg(R), OptionalReg(O) {}
-};
-
 struct SysAliasImm : SysAlias {
   uint16_t ImmValue;
   constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I)

llvm/test/MC/AArch64/arm64-aliases.s

@@ -512,6 +512,20 @@ foo:
   sys #4, c8, c3, #6
 ; CHECK: tlbi vmalls12e1is
 
+; Check that all 5 register bits are set (0x31):
+;    (from Arm ARM regarding TLBI instructions without operands)
+;    "Rt should be encoded as 0b11111. If the Rt field is not set to 0b11111,
+;     it is CONSTRAINED UNPREDICTABLE whether:
+;       * The instruction is UNDEFINED.
+;       * The instruction behaves as if the Rt field is set to 0b11111."
+;
+; Do not disassemble this to `tlbi` but a SYS alias instead
+;
+  sys #4, c8, c7, #6, x30
+; CHECK: sys #0x4, c8, c7, #0x6, x30
+  sys #4, c8, c7, #6, x31
+; CHECK: tlbi vmalls12e1
+
   ic ialluis
 ; CHECK: ic ialluis                 ; encoding: [0x1f,0x71,0x08,0xd5]
   ic iallu