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[Xtensa] Implement Xtensa Floating Point Option.
1 parent 377ec36 commit 41853e4

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14 files changed

+1384
-6
lines changed

14 files changed

+1384
-6
lines changed

‎llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp‎

Lines changed: 38 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -113,6 +113,44 @@ static DecodeStatus DecodeMR23RegisterClass(MCInst &Inst, uint64_t RegNo,
113113
return MCDisassembler::Success;
114114
}
115115

116+
static const unsigned FPRDecoderTable[] = {
117+
Xtensa::F0, Xtensa::F1, Xtensa::F2, Xtensa::F3, Xtensa::F4, Xtensa::F5,
118+
Xtensa::F6, Xtensa::F7, Xtensa::F8, Xtensa::F9, Xtensa::F10, Xtensa::F11,
119+
Xtensa::F12, Xtensa::F13, Xtensa::F14, Xtensa::F15};
120+
121+
static DecodeStatus DecodeFPRRegisterClass(MCInst &Inst, uint64_t RegNo,
122+
uint64_t Address,
123+
const void *Decoder) {
124+
if (RegNo >= std::size(FPRDecoderTable))
125+
return MCDisassembler::Fail;
126+
127+
unsigned Reg = FPRDecoderTable[RegNo];
128+
Inst.addOperand(MCOperand::createReg(Reg));
129+
return MCDisassembler::Success;
130+
}
131+
132+
static const unsigned URDecoderTable[] = {Xtensa::FCR, 232, Xtensa::FSR, 233};
133+
134+
static DecodeStatus DecodeURRegisterClass(MCInst &Inst, uint64_t RegNo,
135+
uint64_t Address,
136+
const void *Decoder) {
137+
const llvm::MCSubtargetInfo STI =
138+
((const MCDisassembler *)Decoder)->getSubtargetInfo();
139+
140+
if (RegNo > 255)
141+
return MCDisassembler::Fail;
142+
143+
for (unsigned i = 0; i < std::size(URDecoderTable); i += 2) {
144+
if (URDecoderTable[i + 1] == RegNo) {
145+
unsigned Reg = URDecoderTable[i];
146+
Inst.addOperand(MCOperand::createReg(Reg));
147+
return MCDisassembler::Success;
148+
}
149+
}
150+
151+
return MCDisassembler::Fail;
152+
}
153+
116154
const MCPhysReg SRDecoderTable[] = {
117155
Xtensa::SAR, 3, Xtensa::ACCLO, 16, Xtensa::ACCHI, 17,
118156
Xtensa::M0, 32, Xtensa::M1, 33, Xtensa::M2, 34,

‎llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -307,6 +307,11 @@ XtensaMCCodeEmitter::getMemRegEncoding(const MCInst &MI, unsigned OpNo,
307307
case Xtensa::L32I:
308308
case Xtensa::S32I_N:
309309
case Xtensa::L32I_N:
310+
case Xtensa::SSI:
311+
case Xtensa::SSIP:
312+
case Xtensa::LSI:
313+
case Xtensa::LSIP:
314+
310315
if (Res & 0x3) {
311316
report_fatal_error("Unexpected operand value!");
312317
}

‎llvm/lib/Target/Xtensa/XtensaCallingConv.td‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515
def RetCC_Xtensa : CallingConv<[
1616
// First two return values go in a2, a3, a4, a5
1717
CCIfType<[i32], CCAssignToReg<[A2, A3, A4, A5]>>,
18+
CCIfType<[f32], CCAssignToReg<[A2, A3, A4, A5]>>,
1819
CCIfType<[i64], CCAssignToRegWithShadow<[A2, A4], [A3, A5]>>
1920
]>;
2021

‎llvm/lib/Target/Xtensa/XtensaFeatures.td‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,11 @@ def FeatureDensity : SubtargetFeature<"density", "HasDensity", "true",
88
def HasDensity : Predicate<"Subtarget->hasDensity()">,
99
AssemblerPredicate<(all_of FeatureDensity)>;
1010

11+
def FeatureSingleFloat : SubtargetFeature<"fp", "HasSingleFloat", "true",
12+
"Enable Xtensa Single FP instructions">;
13+
def HasSingleFloat : Predicate<"Subtarget->hasSingleFloat()">,
14+
AssemblerPredicate<(all_of FeatureSingleFloat)>;
15+
1116
def FeatureWindowed : SubtargetFeature<"windowed", "HasWindowed", "true",
1217
"Enable Xtensa Windowed Register option">;
1318
def HasWindowed : Predicate<"Subtarget->hasWindowed()">,

‎llvm/lib/Target/Xtensa/XtensaISelLowering.cpp‎

Lines changed: 167 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -58,6 +58,10 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &TM,
5858
// Set up the register classes.
5959
addRegisterClass(MVT::i32, &Xtensa::ARRegClass);
6060

61+
if (Subtarget.hasSingleFloat()) {
62+
addRegisterClass(MVT::f32, &Xtensa::FPRRegClass);
63+
}
64+
6165
if (Subtarget.hasBoolean()) {
6266
addRegisterClass(MVT::v1i1, &Xtensa::BRRegClass);
6367
}
@@ -71,6 +75,8 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &TM,
7175

7276
setOperationAction(ISD::Constant, MVT::i32, Custom);
7377
setOperationAction(ISD::Constant, MVT::i64, Expand);
78+
setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
79+
setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
7480

7581
setBooleanContents(ZeroOrOneBooleanContent);
7682

@@ -108,7 +114,10 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &TM,
108114

109115
setOperationAction(ISD::SELECT, MVT::i32, Expand);
110116
setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
117+
setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
118+
111119
setOperationAction(ISD::SETCC, MVT::i32, Expand);
120+
setOperationAction(ISD::SETCC, MVT::f32, Expand);
112121

113122
setCondCodeAction(ISD::SETGT, MVT::i32, Expand);
114123
setCondCodeAction(ISD::SETLE, MVT::i32, Expand);
@@ -157,6 +166,103 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &TM,
157166
setOperationAction(ISD::VACOPY, MVT::Other, Custom);
158167
setOperationAction(ISD::VAEND, MVT::Other, Expand);
159168

169+
// Handle floating-point types.
170+
for (unsigned I = MVT::FIRST_FP_VALUETYPE; I <= MVT::LAST_FP_VALUETYPE; ++I) {
171+
MVT VT = MVT::SimpleValueType(I);
172+
if (isTypeLegal(VT)) {
173+
// We can use FI for FRINT.
174+
// setOperationAction(ISD::FRINT, VT, Legal);
175+
if (VT.getSizeInBits() == 32 && Subtarget.hasSingleFloat()) {
176+
setOperationAction(ISD::FABS, VT, Legal);
177+
setOperationAction(ISD::FADD, VT, Legal);
178+
setOperationAction(ISD::FSUB, VT, Legal);
179+
setOperationAction(ISD::FMA, VT, Legal);
180+
setOperationAction(ISD::FMUL, VT, Legal);
181+
setOperationAction(ISD::FNEG, VT, Legal);
182+
} else {
183+
setOperationAction(ISD::FABS, VT, Expand);
184+
setOperationAction(ISD::FADD, VT, Expand);
185+
setOperationAction(ISD::FSUB, VT, Expand);
186+
setOperationAction(ISD::FMA, VT, Expand);
187+
setOperationAction(ISD::FMUL, VT, Expand);
188+
setOperationAction(ISD::FNEG, VT, Expand);
189+
}
190+
191+
// TODO: once implemented in InstrInfo uncomment
192+
setOperationAction(ISD::FSQRT, VT, Expand);
193+
194+
// No special instructions for these.
195+
setOperationAction(ISD::FCBRT, VT, Expand);
196+
setOperationAction(ISD::FCEIL, VT, Expand);
197+
setOperationAction(ISD::FSIN, VT, Expand);
198+
setOperationAction(ISD::FCOS, VT, Expand);
199+
setOperationAction(ISD::FREM, VT, Expand);
200+
setOperationAction(ISD::FDIV, VT, Expand);
201+
setOperationAction(ISD::FEXP, VT, Expand);
202+
setOperationAction(ISD::FEXP2, VT, Expand);
203+
setOperationAction(ISD::FFLOOR, VT, Expand);
204+
setOperationAction(ISD::FLOG, VT, Expand);
205+
setOperationAction(ISD::FLOG2, VT, Expand);
206+
setOperationAction(ISD::FLOG10, VT, Expand);
207+
setOperationAction(ISD::FMAXIMUM, VT, Expand);
208+
setOperationAction(ISD::FMINIMUM, VT, Expand);
209+
setOperationAction(ISD::FMAXNUM, VT, Expand);
210+
setOperationAction(ISD::FMINNUM, VT, Expand);
211+
setOperationAction(ISD::FNEARBYINT, VT, Expand);
212+
setOperationAction(ISD::FPOW, VT, Expand);
213+
setOperationAction(ISD::FPOWI, VT, Expand);
214+
setOperationAction(ISD::FRINT, VT, Expand);
215+
setOperationAction(ISD::FROUND, VT, Expand);
216+
setOperationAction(ISD::FSINCOS, VT, Expand);
217+
setOperationAction(ISD::FSQRT, VT, Expand);
218+
setOperationAction(ISD::FTRUNC, VT, Expand);
219+
setOperationAction(ISD::LLRINT, VT, Expand);
220+
setOperationAction(ISD::LLROUND, VT, Expand);
221+
setOperationAction(ISD::LRINT, VT, Expand);
222+
setOperationAction(ISD::LROUND, VT, Expand);
223+
}
224+
}
225+
226+
// Handle floating-point types.
227+
if (Subtarget.hasSingleFloat()) {
228+
setOperationAction(ISD::BITCAST, MVT::i32, Legal);
229+
setOperationAction(ISD::BITCAST, MVT::f32, Legal);
230+
setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
231+
setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
232+
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
233+
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
234+
235+
setCondCodeAction(ISD::SETOGT, MVT::f32, Expand);
236+
setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
237+
setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
238+
setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
239+
setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
240+
} else {
241+
setOperationAction(ISD::BITCAST, MVT::i32, Expand);
242+
setOperationAction(ISD::BITCAST, MVT::f32, Expand);
243+
setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
244+
setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
245+
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
246+
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Expand);
247+
}
248+
setOperationAction(ISD::FMA, MVT::f64, Expand);
249+
setOperationAction(ISD::SETCC, MVT::f64, Expand);
250+
setOperationAction(ISD::BITCAST, MVT::i64, Expand);
251+
setOperationAction(ISD::BITCAST, MVT::f64, Expand);
252+
setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
253+
setOperationAction(ISD::SINT_TO_FP, MVT::i64, Expand);
254+
setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
255+
setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
256+
257+
// Needed so that we don't try to implement f128 constant loads using
258+
// a load-and-extend of a f80 constant (in cases where the constant
259+
// would fit in an f80).
260+
for (MVT VT : MVT::fp_valuetypes())
261+
setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
262+
263+
// Floating-point truncation and stores need to be done separately.
264+
setTruncStoreAction(MVT::f64, MVT::f32, Expand);
265+
160266
// Compute derived properties from the register classes
161267
computeRegisterProperties(STI.getRegisterInfo());
162268
}
@@ -167,6 +273,11 @@ bool XtensaTargetLowering::isOffsetFoldingLegal(
167273
return false;
168274
}
169275

276+
bool XtensaTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
277+
bool ForCodeSize) const {
278+
return false;
279+
}
280+
170281
//===----------------------------------------------------------------------===//
171282
// Inline asm support
172283
//===----------------------------------------------------------------------===//
@@ -317,6 +428,16 @@ static bool CC_Xtensa_Custom(unsigned ValNo, MVT ValVT, MVT LocVT,
317428
return false;
318429
}
319430

431+
/// Return the register type for a given MVT
432+
MVT XtensaTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
433+
CallingConv::ID CC,
434+
EVT VT) const {
435+
if (VT.isFloatingPoint())
436+
return MVT::i32;
437+
438+
return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
439+
}
440+
320441
CCAssignFn *XtensaTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
321442
bool IsVarArg) const {
322443
return CC_Xtensa_Custom;
@@ -797,6 +918,21 @@ SDValue XtensaTargetLowering::LowerImmediate(SDValue Op,
797918
return Op;
798919
}
799920

921+
SDValue XtensaTargetLowering::LowerImmediateFP(SDValue Op,
922+
SelectionDAG &DAG) const {
923+
const ConstantFPSDNode *CN = cast<ConstantFPSDNode>(Op);
924+
SDLoc DL(CN);
925+
APFloat apval = CN->getValueAPF();
926+
int64_t value = llvm::bit_cast<uint32_t>(CN->getValueAPF().convertToFloat());
927+
if (Op.getValueType() == MVT::f32) {
928+
Type *Ty = Type::getInt32Ty(*DAG.getContext());
929+
Constant *CV = ConstantInt::get(Ty, value);
930+
SDValue CP = DAG.getConstantPool(CV, MVT::i32);
931+
return DAG.getNode(ISD::BITCAST, DL, MVT::f32, CP);
932+
}
933+
return Op;
934+
}
935+
800936
SDValue XtensaTargetLowering::LowerGlobalAddress(SDValue Op,
801937
SelectionDAG &DAG) const {
802938
const GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
@@ -1230,6 +1366,8 @@ SDValue XtensaTargetLowering::LowerOperation(SDValue Op,
12301366
return LowerBR_JT(Op, DAG);
12311367
case ISD::Constant:
12321368
return LowerImmediate(Op, DAG);
1369+
case ISD::ConstantFP:
1370+
return LowerImmediateFP(Op, DAG);
12331371
case ISD::RETURNADDR:
12341372
return LowerRETURNADDR(Op, DAG);
12351373
case ISD::GlobalAddress:
@@ -1293,6 +1431,26 @@ const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode) const {
12931431
return "XtensaISD::SRCL";
12941432
case XtensaISD::SRCR:
12951433
return "XtensaISD::SRCR";
1434+
case XtensaISD::CMPUO:
1435+
return "XtensaISD::CMPUO";
1436+
case XtensaISD::CMPUEQ:
1437+
return "XtensaISD::CMPUEQ";
1438+
case XtensaISD::CMPULE:
1439+
return "XtensaISD::CMPULE";
1440+
case XtensaISD::CMPULT:
1441+
return "XtensaISD::CMPULT";
1442+
case XtensaISD::CMPOEQ:
1443+
return "XtensaISD::CMPOEQ";
1444+
case XtensaISD::CMPOLE:
1445+
return "XtensaISD::CMPOLE";
1446+
case XtensaISD::CMPOLT:
1447+
return "XtensaISD::CMPOLT";
1448+
case XtensaISD::MADD:
1449+
return "XtensaISD::MADD";
1450+
case XtensaISD::MSUB:
1451+
return "XtensaISD::MSUB";
1452+
case XtensaISD::MOVS:
1453+
return "XtensaISD::MOVS";
12961454
}
12971455
return nullptr;
12981456
}
@@ -1377,11 +1535,19 @@ MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter(
13771535
case Xtensa::S16I:
13781536
case Xtensa::S32I:
13791537
case Xtensa::S32I_N:
1538+
case Xtensa::SSI:
1539+
case Xtensa::SSIP:
1540+
case Xtensa::SSX:
1541+
case Xtensa::SSXP:
13801542
case Xtensa::L8UI:
13811543
case Xtensa::L16SI:
13821544
case Xtensa::L16UI:
13831545
case Xtensa::L32I:
1384-
case Xtensa::L32I_N: {
1546+
case Xtensa::L32I_N:
1547+
case Xtensa::LSI:
1548+
case Xtensa::LSIP:
1549+
case Xtensa::LSX:
1550+
case Xtensa::LSXP: {
13851551
// Insert memory wait instruction "memw" before volatile load/store as it is
13861552
// implemented in gcc. If memoperands is empty then assume that it aslo
13871553
// maybe volatile load/store and insert "memw".

‎llvm/lib/Target/Xtensa/XtensaISelLowering.h‎

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -56,6 +56,21 @@ enum {
5656
SRCL,
5757
// Shift Right Combined
5858
SRCR,
59+
60+
// Floating point unordered compare conditions
61+
CMPUEQ,
62+
CMPULE,
63+
CMPULT,
64+
CMPUO,
65+
// Floating point compare conditions
66+
CMPOEQ,
67+
CMPOLE,
68+
CMPOLT,
69+
// FP multipy-add/sub
70+
MADD,
71+
MSUB,
72+
// FP move
73+
MOVS,
5974
};
6075
}
6176

@@ -70,6 +85,9 @@ class XtensaTargetLowering : public TargetLowering {
7085
return LHSTy.getSizeInBits() <= 32 ? MVT::i32 : MVT::i64;
7186
}
7287

88+
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,
89+
EVT VT) const override;
90+
7391
EVT getSetCCResultType(const DataLayout &, LLVMContext &,
7492
EVT VT) const override {
7593
if (!VT.isVector())
@@ -81,6 +99,9 @@ class XtensaTargetLowering : public TargetLowering {
8199

82100
const char *getTargetNodeName(unsigned Opcode) const override;
83101

102+
bool isFPImmLegal(const APFloat &Imm, EVT VT,
103+
bool ForCodeSize) const override;
104+
84105
std::pair<unsigned, const TargetRegisterClass *>
85106
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
86107
StringRef Constraint, MVT VT) const override;
@@ -133,6 +154,8 @@ class XtensaTargetLowering : public TargetLowering {
133154

134155
SDValue LowerImmediate(SDValue Op, SelectionDAG &DAG) const;
135156

157+
SDValue LowerImmediateFP(SDValue Op, SelectionDAG &DAG) const;
158+
136159
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
137160

138161
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;

‎llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp‎

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -151,11 +151,15 @@ void XtensaInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC,
151151
unsigned &LoadOpcode,
152152
unsigned &StoreOpcode,
153153
int64_t offset) const {
154-
assert((RC == &Xtensa::ARRegClass) &&
155-
"Unsupported regclass to load or store");
156-
157-
LoadOpcode = Xtensa::L32I;
158-
StoreOpcode = Xtensa::S32I;
154+
if (RC == &Xtensa::ARRegClass) {
155+
LoadOpcode = Xtensa::L32I;
156+
StoreOpcode = Xtensa::S32I;
157+
} else if (RC == &Xtensa::FPRRegClass) {
158+
LoadOpcode = Xtensa::LSI;
159+
StoreOpcode = Xtensa::SSI;
160+
} else {
161+
llvm_unreachable("Unsupported regclass to load or store");
162+
}
159163
}
160164

161165
void XtensaInstrInfo::loadImmediate(MachineBasicBlock &MBB,

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