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[RISCV][GlobalIsel] Lower G_FMINIMUMNUM, G_FMAXIMUMNUM (#157295)
Similar to the implementation in #104411 , the `fmin.s`/`fmax.s` instructions follow IEEE 754-2019 semantics, and `G_FMINIMUMNUM`/`G_FMAXIMUMNUM` are legal.
1 parent 8a8a810 commit 41d7ae8

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8 files changed

+325
-72
lines changed

8 files changed

+325
-72
lines changed

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -487,6 +487,10 @@ static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
487487
RTLIBCASE(FMIN_F);
488488
case TargetOpcode::G_FMAXNUM:
489489
RTLIBCASE(FMAX_F);
490+
case TargetOpcode::G_FMINIMUMNUM:
491+
RTLIBCASE(FMINIMUM_NUM_F);
492+
case TargetOpcode::G_FMAXIMUMNUM:
493+
RTLIBCASE(FMAXIMUM_NUM_F);
490494
case TargetOpcode::G_FSQRT:
491495
RTLIBCASE(SQRT_F);
492496
case TargetOpcode::G_FRINT:
@@ -1307,6 +1311,8 @@ LegalizerHelper::libcall(MachineInstr &MI, LostDebugLocObserver &LocObserver) {
13071311
case TargetOpcode::G_FFLOOR:
13081312
case TargetOpcode::G_FMINNUM:
13091313
case TargetOpcode::G_FMAXNUM:
1314+
case TargetOpcode::G_FMINIMUMNUM:
1315+
case TargetOpcode::G_FMAXIMUMNUM:
13101316
case TargetOpcode::G_FSQRT:
13111317
case TargetOpcode::G_FRINT:
13121318
case TargetOpcode::G_FNEARBYINT:

‎llvm/lib/CodeGen/GlobalISel/Utils.cpp‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1758,9 +1758,11 @@ bool llvm::isPreISelGenericFloatingPointOpcode(unsigned Opc) {
17581758
case TargetOpcode::G_FMA:
17591759
case TargetOpcode::G_FMAD:
17601760
case TargetOpcode::G_FMAXIMUM:
1761+
case TargetOpcode::G_FMAXIMUMNUM:
17611762
case TargetOpcode::G_FMAXNUM:
17621763
case TargetOpcode::G_FMAXNUM_IEEE:
17631764
case TargetOpcode::G_FMINIMUM:
1765+
case TargetOpcode::G_FMINIMUMNUM:
17641766
case TargetOpcode::G_FMINNUM:
17651767
case TargetOpcode::G_FMINNUM_IEEE:
17661768
case TargetOpcode::G_FMUL:

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -511,8 +511,9 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
511511
// FP Operations
512512

513513
// FIXME: Support s128 for rv32 when libcall handling is able to use sret.
514-
getActionDefinitionsBuilder(
515-
{G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FMA, G_FSQRT, G_FMAXNUM, G_FMINNUM})
514+
getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FMA, G_FSQRT,
515+
G_FMAXNUM, G_FMINNUM, G_FMAXIMUMNUM,
516+
G_FMINIMUMNUM})
516517
.legalFor(ST.hasStdExtF(), {s32})
517518
.legalFor(ST.hasStdExtD(), {s64})
518519
.legalFor(ST.hasStdExtZfh(), {s16})

‎llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll‎

Lines changed: 90 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -363,6 +363,64 @@ define double @fmax_d(double %a, double %b) nounwind {
363363
ret double %1
364364
}
365365

366+
declare double @llvm.minimumnum.f64(double, double)
367+
368+
define double @fminimumnum_d(double %a, double %b) nounwind {
369+
; CHECKIFD-LABEL: fminimumnum_d:
370+
; CHECKIFD: # %bb.0:
371+
; CHECKIFD-NEXT: fmin.d fa0, fa0, fa1
372+
; CHECKIFD-NEXT: ret
373+
;
374+
; RV32I-LABEL: fminimumnum_d:
375+
; RV32I: # %bb.0:
376+
; RV32I-NEXT: addi sp, sp, -16
377+
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
378+
; RV32I-NEXT: call fminimum_num
379+
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
380+
; RV32I-NEXT: addi sp, sp, 16
381+
; RV32I-NEXT: ret
382+
;
383+
; RV64I-LABEL: fminimumnum_d:
384+
; RV64I: # %bb.0:
385+
; RV64I-NEXT: addi sp, sp, -16
386+
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
387+
; RV64I-NEXT: call fminimum_num
388+
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
389+
; RV64I-NEXT: addi sp, sp, 16
390+
; RV64I-NEXT: ret
391+
%1 = call double @llvm.minimumnum.f64(double %a, double %b)
392+
ret double %1
393+
}
394+
395+
declare double @llvm.maximumnum.f64(double, double)
396+
397+
define double @fmaximumnum_d(double %a, double %b) nounwind {
398+
; CHECKIFD-LABEL: fmaximumnum_d:
399+
; CHECKIFD: # %bb.0:
400+
; CHECKIFD-NEXT: fmax.d fa0, fa0, fa1
401+
; CHECKIFD-NEXT: ret
402+
;
403+
; RV32I-LABEL: fmaximumnum_d:
404+
; RV32I: # %bb.0:
405+
; RV32I-NEXT: addi sp, sp, -16
406+
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
407+
; RV32I-NEXT: call fmaximum_num
408+
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
409+
; RV32I-NEXT: addi sp, sp, 16
410+
; RV32I-NEXT: ret
411+
;
412+
; RV64I-LABEL: fmaximumnum_d:
413+
; RV64I: # %bb.0:
414+
; RV64I-NEXT: addi sp, sp, -16
415+
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
416+
; RV64I-NEXT: call fmaximum_num
417+
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
418+
; RV64I-NEXT: addi sp, sp, 16
419+
; RV64I-NEXT: ret
420+
%1 = call double @llvm.maximumnum.f64(double %a, double %b)
421+
ret double %1
422+
}
423+
366424
declare double @llvm.fma.f64(double, double, double)
367425

368426
define double @fmadd_d(double %a, double %b, double %c) nounwind {
@@ -420,8 +478,8 @@ define double @fmsub_d(double %a, double %b, double %c) nounwind {
420478
; RV32I-NEXT: mv s2, a2
421479
; RV32I-NEXT: mv s3, a3
422480
; RV32I-NEXT: mv a0, a4
423-
; RV32I-NEXT: lui a1, %hi(.LCPI12_0)
424-
; RV32I-NEXT: addi a1, a1, %lo(.LCPI12_0)
481+
; RV32I-NEXT: lui a1, %hi(.LCPI14_0)
482+
; RV32I-NEXT: addi a1, a1, %lo(.LCPI14_0)
425483
; RV32I-NEXT: lw a2, 0(a1)
426484
; RV32I-NEXT: lw a3, 4(a1)
427485
; RV32I-NEXT: mv a1, a5
@@ -450,8 +508,8 @@ define double @fmsub_d(double %a, double %b, double %c) nounwind {
450508
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
451509
; RV64I-NEXT: mv s0, a0
452510
; RV64I-NEXT: mv s1, a1
453-
; RV64I-NEXT: lui a0, %hi(.LCPI12_0)
454-
; RV64I-NEXT: ld a1, %lo(.LCPI12_0)(a0)
511+
; RV64I-NEXT: lui a0, %hi(.LCPI14_0)
512+
; RV64I-NEXT: ld a1, %lo(.LCPI14_0)(a0)
455513
; RV64I-NEXT: mv a0, a2
456514
; RV64I-NEXT: call __adddf3
457515
; RV64I-NEXT: li a1, -1
@@ -503,8 +561,8 @@ define double @fnmadd_d(double %a, double %b, double %c) nounwind {
503561
; RV32I-NEXT: mv s0, a2
504562
; RV32I-NEXT: mv s1, a3
505563
; RV32I-NEXT: mv s2, a4
506-
; RV32I-NEXT: lui a2, %hi(.LCPI13_0)
507-
; RV32I-NEXT: addi a2, a2, %lo(.LCPI13_0)
564+
; RV32I-NEXT: lui a2, %hi(.LCPI15_0)
565+
; RV32I-NEXT: addi a2, a2, %lo(.LCPI15_0)
508566
; RV32I-NEXT: lw s3, 0(a2)
509567
; RV32I-NEXT: lw s4, 4(a2)
510568
; RV32I-NEXT: mv s5, a5
@@ -548,8 +606,8 @@ define double @fnmadd_d(double %a, double %b, double %c) nounwind {
548606
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
549607
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
550608
; RV64I-NEXT: mv s0, a1
551-
; RV64I-NEXT: lui a1, %hi(.LCPI13_0)
552-
; RV64I-NEXT: ld s1, %lo(.LCPI13_0)(a1)
609+
; RV64I-NEXT: lui a1, %hi(.LCPI15_0)
610+
; RV64I-NEXT: ld s1, %lo(.LCPI15_0)(a1)
553611
; RV64I-NEXT: mv s2, a2
554612
; RV64I-NEXT: mv a1, s1
555613
; RV64I-NEXT: call __adddf3
@@ -613,8 +671,8 @@ define double @fnmadd_d_2(double %a, double %b, double %c) nounwind {
613671
; RV32I-NEXT: mv a0, a2
614672
; RV32I-NEXT: mv a1, a3
615673
; RV32I-NEXT: mv s2, a4
616-
; RV32I-NEXT: lui a2, %hi(.LCPI14_0)
617-
; RV32I-NEXT: addi a2, a2, %lo(.LCPI14_0)
674+
; RV32I-NEXT: lui a2, %hi(.LCPI16_0)
675+
; RV32I-NEXT: addi a2, a2, %lo(.LCPI16_0)
618676
; RV32I-NEXT: lw s3, 0(a2)
619677
; RV32I-NEXT: lw s4, 4(a2)
620678
; RV32I-NEXT: mv s5, a5
@@ -658,8 +716,8 @@ define double @fnmadd_d_2(double %a, double %b, double %c) nounwind {
658716
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
659717
; RV64I-NEXT: mv s0, a0
660718
; RV64I-NEXT: mv a0, a1
661-
; RV64I-NEXT: lui a1, %hi(.LCPI14_0)
662-
; RV64I-NEXT: ld s1, %lo(.LCPI14_0)(a1)
719+
; RV64I-NEXT: lui a1, %hi(.LCPI16_0)
720+
; RV64I-NEXT: ld s1, %lo(.LCPI16_0)(a1)
663721
; RV64I-NEXT: mv s2, a2
664722
; RV64I-NEXT: mv a1, s1
665723
; RV64I-NEXT: call __adddf3
@@ -783,8 +841,8 @@ define double @fnmsub_d(double %a, double %b, double %c) nounwind {
783841
; RV32I-NEXT: mv s0, a2
784842
; RV32I-NEXT: mv s1, a3
785843
; RV32I-NEXT: mv s2, a4
786-
; RV32I-NEXT: lui a2, %hi(.LCPI17_0)
787-
; RV32I-NEXT: addi a3, a2, %lo(.LCPI17_0)
844+
; RV32I-NEXT: lui a2, %hi(.LCPI19_0)
845+
; RV32I-NEXT: addi a3, a2, %lo(.LCPI19_0)
788846
; RV32I-NEXT: lw a2, 0(a3)
789847
; RV32I-NEXT: lw a3, 4(a3)
790848
; RV32I-NEXT: mv s3, a5
@@ -811,8 +869,8 @@ define double @fnmsub_d(double %a, double %b, double %c) nounwind {
811869
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
812870
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
813871
; RV64I-NEXT: mv s0, a1
814-
; RV64I-NEXT: lui a1, %hi(.LCPI17_0)
815-
; RV64I-NEXT: ld a1, %lo(.LCPI17_0)(a1)
872+
; RV64I-NEXT: lui a1, %hi(.LCPI19_0)
873+
; RV64I-NEXT: ld a1, %lo(.LCPI19_0)(a1)
816874
; RV64I-NEXT: mv s1, a2
817875
; RV64I-NEXT: call __adddf3
818876
; RV64I-NEXT: li a1, -1
@@ -860,8 +918,8 @@ define double @fnmsub_d_2(double %a, double %b, double %c) nounwind {
860918
; RV32I-NEXT: mv a0, a2
861919
; RV32I-NEXT: mv a1, a3
862920
; RV32I-NEXT: mv s2, a4
863-
; RV32I-NEXT: lui a2, %hi(.LCPI18_0)
864-
; RV32I-NEXT: addi a3, a2, %lo(.LCPI18_0)
921+
; RV32I-NEXT: lui a2, %hi(.LCPI20_0)
922+
; RV32I-NEXT: addi a3, a2, %lo(.LCPI20_0)
865923
; RV32I-NEXT: lw a2, 0(a3)
866924
; RV32I-NEXT: lw a3, 4(a3)
867925
; RV32I-NEXT: mv s3, a5
@@ -890,8 +948,8 @@ define double @fnmsub_d_2(double %a, double %b, double %c) nounwind {
890948
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
891949
; RV64I-NEXT: mv s0, a0
892950
; RV64I-NEXT: mv a0, a1
893-
; RV64I-NEXT: lui a1, %hi(.LCPI18_0)
894-
; RV64I-NEXT: ld a1, %lo(.LCPI18_0)(a1)
951+
; RV64I-NEXT: lui a1, %hi(.LCPI20_0)
952+
; RV64I-NEXT: ld a1, %lo(.LCPI20_0)(a1)
895953
; RV64I-NEXT: mv s1, a2
896954
; RV64I-NEXT: call __adddf3
897955
; RV64I-NEXT: li a1, -1
@@ -985,8 +1043,8 @@ define double @fmsub_d_contract(double %a, double %b, double %c) nounwind {
9851043
; RV32I-NEXT: mv s2, a2
9861044
; RV32I-NEXT: mv s3, a3
9871045
; RV32I-NEXT: mv a0, a4
988-
; RV32I-NEXT: lui a1, %hi(.LCPI20_0)
989-
; RV32I-NEXT: addi a1, a1, %lo(.LCPI20_0)
1046+
; RV32I-NEXT: lui a1, %hi(.LCPI22_0)
1047+
; RV32I-NEXT: addi a1, a1, %lo(.LCPI22_0)
9901048
; RV32I-NEXT: lw a2, 0(a1)
9911049
; RV32I-NEXT: lw a3, 4(a1)
9921050
; RV32I-NEXT: mv a1, a5
@@ -1020,8 +1078,8 @@ define double @fmsub_d_contract(double %a, double %b, double %c) nounwind {
10201078
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
10211079
; RV64I-NEXT: mv s0, a0
10221080
; RV64I-NEXT: mv s1, a1
1023-
; RV64I-NEXT: lui a0, %hi(.LCPI20_0)
1024-
; RV64I-NEXT: ld a1, %lo(.LCPI20_0)(a0)
1081+
; RV64I-NEXT: lui a0, %hi(.LCPI22_0)
1082+
; RV64I-NEXT: ld a1, %lo(.LCPI22_0)(a0)
10251083
; RV64I-NEXT: mv a0, a2
10261084
; RV64I-NEXT: call __adddf3
10271085
; RV64I-NEXT: mv s2, a0
@@ -1080,8 +1138,8 @@ define double @fnmadd_d_contract(double %a, double %b, double %c) nounwind {
10801138
; RV32I-NEXT: mv s0, a2
10811139
; RV32I-NEXT: mv s1, a3
10821140
; RV32I-NEXT: mv s2, a4
1083-
; RV32I-NEXT: lui a2, %hi(.LCPI21_0)
1084-
; RV32I-NEXT: addi a2, a2, %lo(.LCPI21_0)
1141+
; RV32I-NEXT: lui a2, %hi(.LCPI23_0)
1142+
; RV32I-NEXT: addi a2, a2, %lo(.LCPI23_0)
10851143
; RV32I-NEXT: lw s3, 0(a2)
10861144
; RV32I-NEXT: lw s4, 4(a2)
10871145
; RV32I-NEXT: mv s5, a5
@@ -1135,8 +1193,8 @@ define double @fnmadd_d_contract(double %a, double %b, double %c) nounwind {
11351193
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
11361194
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
11371195
; RV64I-NEXT: mv s0, a1
1138-
; RV64I-NEXT: lui a1, %hi(.LCPI21_0)
1139-
; RV64I-NEXT: ld s1, %lo(.LCPI21_0)(a1)
1196+
; RV64I-NEXT: lui a1, %hi(.LCPI23_0)
1197+
; RV64I-NEXT: ld s1, %lo(.LCPI23_0)(a1)
11401198
; RV64I-NEXT: mv s2, a2
11411199
; RV64I-NEXT: mv a1, s1
11421200
; RV64I-NEXT: call __adddf3
@@ -1205,8 +1263,8 @@ define double @fnmsub_d_contract(double %a, double %b, double %c) nounwind {
12051263
; RV32I-NEXT: mv s0, a2
12061264
; RV32I-NEXT: mv s1, a3
12071265
; RV32I-NEXT: mv s2, a4
1208-
; RV32I-NEXT: lui a2, %hi(.LCPI22_0)
1209-
; RV32I-NEXT: addi a2, a2, %lo(.LCPI22_0)
1266+
; RV32I-NEXT: lui a2, %hi(.LCPI24_0)
1267+
; RV32I-NEXT: addi a2, a2, %lo(.LCPI24_0)
12101268
; RV32I-NEXT: lw s3, 0(a2)
12111269
; RV32I-NEXT: lw s4, 4(a2)
12121270
; RV32I-NEXT: mv s5, a5
@@ -1251,8 +1309,8 @@ define double @fnmsub_d_contract(double %a, double %b, double %c) nounwind {
12511309
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
12521310
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
12531311
; RV64I-NEXT: mv s0, a1
1254-
; RV64I-NEXT: lui a1, %hi(.LCPI22_0)
1255-
; RV64I-NEXT: ld s1, %lo(.LCPI22_0)(a1)
1312+
; RV64I-NEXT: lui a1, %hi(.LCPI24_0)
1313+
; RV64I-NEXT: ld s1, %lo(.LCPI24_0)(a1)
12561314
; RV64I-NEXT: mv s2, a2
12571315
; RV64I-NEXT: mv a1, s1
12581316
; RV64I-NEXT: call __adddf3

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