Use IndexedMap where it is straightforward to do so

Author: s-barannikov

llvm/include/llvm/CodeGen/RDFRegisters.h

@@ -10,6 +10,7 @@
 #define LLVM_CODEGEN_RDFREGISTERS_H
 
 #include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/IndexedMap.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/iterator_range.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
@@ -154,8 +155,7 @@ struct PhysicalRegisterInfo {
   std::set<RegisterId> getAliasSet(RegisterId Reg) const;
 
   RegisterRef getRefForUnit(MCRegUnit U) const {
-    return RegisterRef(UnitInfos[static_cast<unsigned>(U)].Reg,
-                       UnitInfos[static_cast<unsigned>(U)].Mask);
+    return RegisterRef(UnitInfos[U].Reg, UnitInfos[U].Mask);
   }
 
   const BitVector &getMaskUnits(RegisterId MaskId) const {
@@ -165,7 +165,7 @@ struct PhysicalRegisterInfo {
   std::set<RegisterId> getUnits(RegisterRef RR) const;
 
   const BitVector &getUnitAliases(MCRegUnit U) const {
-    return AliasInfos[static_cast<unsigned>(U)].Regs;
+    return AliasInfos[U].Regs;
   }
 
   RegisterRef mapTo(RegisterRef RR, unsigned R) const;
@@ -195,9 +195,9 @@ struct PhysicalRegisterInfo {
   const TargetRegisterInfo &TRI;
   IndexedSet<const uint32_t *> RegMasks;
   std::vector<RegInfo> RegInfos;
-  std::vector<UnitInfo> UnitInfos;
+  IndexedMap<UnitInfo, MCRegUnitToIndex> UnitInfos;
   std::vector<MaskInfo> MaskInfos;
-  std::vector<AliasInfo> AliasInfos;
+  IndexedMap<AliasInfo, MCRegUnitToIndex> AliasInfos;
 };
 
 struct RegisterRefEqualTo {

llvm/lib/CodeGen/RDFRegisters.cpp

@@ -47,19 +47,19 @@ PhysicalRegisterInfo::PhysicalRegisterInfo(const TargetRegisterInfo &tri,
   UnitInfos.resize(TRI.getNumRegUnits());
 
   for (MCRegUnit U : TRI.regunits()) {
-    if (UnitInfos[static_cast<unsigned>(U)].Reg != 0)
+    if (UnitInfos[U].Reg != 0)
       continue;
     MCRegUnitRootIterator R(U, &TRI);
     assert(R.isValid());
     RegisterId F = *R;
     ++R;
     if (R.isValid()) {
-      UnitInfos[static_cast<unsigned>(U)].Mask = LaneBitmask::getAll();
-      UnitInfos[static_cast<unsigned>(U)].Reg = F;
+      UnitInfos[U].Mask = LaneBitmask::getAll();
+      UnitInfos[U].Reg = F;
     } else {
       for (MCRegUnitMaskIterator I(F, &TRI); I.isValid(); ++I) {
         std::pair<MCRegUnit, LaneBitmask> P = *I;
-        UnitInfo &UI = UnitInfos[static_cast<unsigned>(P.first)];
+        UnitInfo &UI = UnitInfos[P.first];
         UI.Reg = F;
         UI.Mask = P.second;
       }
@@ -93,7 +93,7 @@ PhysicalRegisterInfo::PhysicalRegisterInfo(const TargetRegisterInfo &tri,
     for (MCRegUnitRootIterator R(U, &TRI); R.isValid(); ++R)
       for (MCPhysReg S : TRI.superregs_inclusive(*R))
         AS.set(S);
-    AliasInfos[static_cast<unsigned>(U)].Regs = AS;
+    AliasInfos[U].Regs = AS;
   }
 }