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fixup! Limit the condition to build_vector with *all* operands being extraction from first element
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+143
-140
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3 files changed

+143
-140
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 17 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -4514,9 +4514,15 @@ static SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
45144514
const unsigned Policy = RISCVVType::TAIL_AGNOSTIC | RISCVVType::MASK_AGNOSTIC;
45154515

45164516
// General case: splat the first operand and slide other operands down one
4517-
// by one to form a vector. Alternatively, if the last operand is an
4518-
// extraction from element 0 of a vector, we can use that vector as the start
4519-
// value and slide up instead of slide down. Such that we can avoid the splat.
4517+
// by one to form a vector. Alternatively, if every operand is an
4518+
// extraction from element 0 of a vector, we use that vector from the last
4519+
// extraction as the start value and slide up instead of slide down. Such that
4520+
// (1) we can avoid the initial splat (2) we can turn those vslide1up into
4521+
// vslideup of 1 later and eliminate the vector to scalar movement, which is
4522+
// something we cannot do with vslide1down/vslidedown.
4523+
// Of course, using vslide1up/vslideup might increase the register pressure,
4524+
// and that's why we conservatively limit to cases where every operands is an
4525+
// extraction from first element.
45204526
SmallVector<SDValue> Operands(Op->op_begin(), Op->op_end());
45214527
SDValue EVec;
45224528
bool SlideUp = false;
@@ -4529,13 +4535,15 @@ static SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
45294535
Mask, VL, Policy);
45304536
};
45314537

4532-
// Find the first first non-undef from the tail.
4533-
auto ItLastNonUndef = find_if(Operands.rbegin(), Operands.rend(),
4534-
[](SDValue V) { return !V.isUndef(); });
4535-
if (ItLastNonUndef != Operands.rend()) {
4538+
// The reason we don't use all_of here is because we're also capturing EVec
4539+
// from the last non-undef operand. If the std::execution_policy of the
4540+
// underlying std::all_of is anything but std::sequenced_policy we might
4541+
// capture the wrong EVec.
4542+
for (SDValue V : Operands) {
45364543
using namespace SDPatternMatch;
4537-
// Check if the last non-undef operand was an extraction.
4538-
SlideUp = sd_match(*ItLastNonUndef, m_ExtractElt(m_Value(EVec), m_Zero()));
4544+
SlideUp = V.isUndef() || sd_match(V, m_ExtractElt(m_Value(EVec), m_Zero()));
4545+
if (!SlideUp)
4546+
break;
45394547
}
45404548

45414549
if (SlideUp) {

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll‎

Lines changed: 114 additions & 119 deletions
Original file line numberDiff line numberDiff line change
@@ -1829,123 +1829,8 @@ define <8 x double> @buildvec_v8f64_zvl512(double %e0, double %e1, double %e2, d
18291829
ret <8 x double> %v7
18301830
}
18311831

1832-
define <8 x double> @buildvec_slideup(<4 x double> %v, double %e0, double %e1, double %e2, double %e3, double %e4, double %e5, double %e6) vscale_range(4, 128) {
1833-
; CHECK-LABEL: buildvec_slideup:
1834-
; CHECK: # %bb.0:
1835-
; CHECK-NEXT: vsetivli zero, 8, e64, m2, ta, ma
1836-
; CHECK-NEXT: vfslide1up.vf v10, v8, fa6
1837-
; CHECK-NEXT: vfslide1up.vf v8, v10, fa5
1838-
; CHECK-NEXT: vfslide1up.vf v10, v8, fa4
1839-
; CHECK-NEXT: vfslide1up.vf v8, v10, fa3
1840-
; CHECK-NEXT: vfslide1up.vf v10, v8, fa2
1841-
; CHECK-NEXT: vfslide1up.vf v12, v10, fa1
1842-
; CHECK-NEXT: vfslide1up.vf v8, v12, fa0
1843-
; CHECK-NEXT: ret
1844-
%v0 = insertelement <8 x double> poison, double %e0, i64 0
1845-
%v1 = insertelement <8 x double> %v0, double %e1, i64 1
1846-
%v2 = insertelement <8 x double> %v1, double %e2, i64 2
1847-
%v3 = insertelement <8 x double> %v2, double %e3, i64 3
1848-
%v4 = insertelement <8 x double> %v3, double %e4, i64 4
1849-
%v5 = insertelement <8 x double> %v4, double %e5, i64 5
1850-
%v6 = insertelement <8 x double> %v5, double %e6, i64 6
1851-
%e7 = extractelement <4 x double> %v, i64 0
1852-
%v7 = insertelement <8 x double> %v6, double %e7, i64 7
1853-
ret <8 x double> %v7
1854-
}
1855-
1856-
define <8 x double> @buildvec_slideup_leading_undef(<4 x double> %v, double %e0, double %e1, double %e2, double %e3, double %e4) vscale_range(4, 128) {
1857-
; CHECK-LABEL: buildvec_slideup_leading_undef:
1858-
; CHECK: # %bb.0:
1859-
; CHECK-NEXT: vsetivli zero, 8, e64, m2, ta, ma
1860-
; CHECK-NEXT: vfslide1up.vf v10, v8, fa4
1861-
; CHECK-NEXT: vfslide1up.vf v8, v10, fa3
1862-
; CHECK-NEXT: vfslide1up.vf v10, v8, fa2
1863-
; CHECK-NEXT: vfslide1up.vf v8, v10, fa1
1864-
; CHECK-NEXT: vfslide1up.vf v10, v8, fa0
1865-
; CHECK-NEXT: vslideup.vi v8, v10, 2
1866-
; CHECK-NEXT: ret
1867-
%v2 = insertelement <8 x double> poison, double %e0, i64 2
1868-
%v3 = insertelement <8 x double> %v2, double %e1, i64 3
1869-
%v4 = insertelement <8 x double> %v3, double %e2, i64 4
1870-
%v5 = insertelement <8 x double> %v4, double %e3, i64 5
1871-
%v6 = insertelement <8 x double> %v5, double %e4, i64 6
1872-
%e5 = extractelement <4 x double> %v, i64 0
1873-
%v7 = insertelement <8 x double> %v6, double %e5, i64 7
1874-
ret <8 x double> %v7
1875-
}
1876-
1877-
define <8 x double> @buildvec_slideup_mid_undef(<4 x double> %v, double %e0, double %e1, double %e2, double %e3, double %e4) vscale_range(4, 128) {
1878-
; CHECK-LABEL: buildvec_slideup_mid_undef:
1879-
; CHECK: # %bb.0:
1880-
; CHECK-NEXT: vsetivli zero, 8, e64, m2, ta, ma
1881-
; CHECK-NEXT: vfslide1up.vf v10, v8, fa4
1882-
; CHECK-NEXT: vfslide1up.vf v8, v10, fa3
1883-
; CHECK-NEXT: vfslide1up.vf v10, v8, fa2
1884-
; CHECK-NEXT: vslideup.vi v8, v10, 2
1885-
; CHECK-NEXT: vfslide1up.vf v10, v8, fa1
1886-
; CHECK-NEXT: vfslide1up.vf v8, v10, fa0
1887-
; CHECK-NEXT: ret
1888-
%v0 = insertelement <8 x double> poison, double %e0, i64 0
1889-
%v1 = insertelement <8 x double> %v0, double %e1, i64 1
1890-
%v4 = insertelement <8 x double> %v1, double %e2, i64 4
1891-
%v5 = insertelement <8 x double> %v4, double %e3, i64 5
1892-
%v6 = insertelement <8 x double> %v5, double %e4, i64 6
1893-
%e5 = extractelement <4 x double> %v, i64 0
1894-
%v7 = insertelement <8 x double> %v6, double %e5, i64 7
1895-
ret <8 x double> %v7
1896-
}
1897-
1898-
define <8 x double> @buildvec_slideup_trailing_undef(<4 x double> %v, double %e0, double %e1, double %e2, double %e3, double %e4) vscale_range(4, 128) {
1899-
; CHECK-LABEL: buildvec_slideup_trailing_undef:
1900-
; CHECK: # %bb.0:
1901-
; CHECK-NEXT: vsetivli zero, 8, e64, m2, ta, ma
1902-
; CHECK-NEXT: vfslide1up.vf v10, v8, fa4
1903-
; CHECK-NEXT: vfslide1up.vf v8, v10, fa3
1904-
; CHECK-NEXT: vfslide1up.vf v10, v8, fa2
1905-
; CHECK-NEXT: vfslide1up.vf v12, v10, fa1
1906-
; CHECK-NEXT: vfslide1up.vf v8, v12, fa0
1907-
; CHECK-NEXT: ret
1908-
%v0 = insertelement <8 x double> poison, double %e0, i64 0
1909-
%v1 = insertelement <8 x double> %v0, double %e1, i64 1
1910-
%v2 = insertelement <8 x double> %v1, double %e2, i64 2
1911-
%v3 = insertelement <8 x double> %v2, double %e3, i64 3
1912-
%v4 = insertelement <8 x double> %v3, double %e4, i64 4
1913-
%e5 = extractelement <4 x double> %v, i64 0
1914-
%v5 = insertelement <8 x double> %v4, double %e5, i64 5
1915-
%v6 = insertelement <8 x double> %v5, double poison, i64 6
1916-
%v7 = insertelement <8 x double> %v6, double poison, i64 7
1917-
ret <8 x double> %v7
1918-
}
1919-
1920-
; Negative test for slideup lowering where the extract_element was not build_vector's last operand.
1921-
define <8 x double> @buildvec_slideup_not_last_element(<4 x double> %v, double %e0, double %e1, double %e2, double %e3, double %e4, double %e5, double %e7) vscale_range(4, 128) {
1922-
; CHECK-LABEL: buildvec_slideup_not_last_element:
1923-
; CHECK: # %bb.0:
1924-
; CHECK-NEXT: vsetivli zero, 8, e64, m2, ta, ma
1925-
; CHECK-NEXT: vfmv.f.s ft0, v8
1926-
; CHECK-NEXT: vfmv.v.f v8, fa0
1927-
; CHECK-NEXT: vfslide1down.vf v8, v8, fa1
1928-
; CHECK-NEXT: vfslide1down.vf v8, v8, fa2
1929-
; CHECK-NEXT: vfslide1down.vf v8, v8, fa3
1930-
; CHECK-NEXT: vfslide1down.vf v8, v8, fa4
1931-
; CHECK-NEXT: vfslide1down.vf v8, v8, fa5
1932-
; CHECK-NEXT: vfslide1down.vf v8, v8, ft0
1933-
; CHECK-NEXT: vfslide1down.vf v8, v8, fa6
1934-
; CHECK-NEXT: ret
1935-
%v0 = insertelement <8 x double> poison, double %e0, i64 0
1936-
%v1 = insertelement <8 x double> %v0, double %e1, i64 1
1937-
%v2 = insertelement <8 x double> %v1, double %e2, i64 2
1938-
%v3 = insertelement <8 x double> %v2, double %e3, i64 3
1939-
%v4 = insertelement <8 x double> %v3, double %e4, i64 4
1940-
%v5 = insertelement <8 x double> %v4, double %e5, i64 5
1941-
%e6 = extractelement <4 x double> %v, i64 0
1942-
%v6 = insertelement <8 x double> %v5, double %e6, i64 6
1943-
%v7 = insertelement <8 x double> %v6, double %e7, i64 7
1944-
ret <8 x double> %v7
1945-
}
1946-
1947-
define <4 x float> @buildvec_vfredusum(float %start, <8 x float> %arg1, <8 x float> %arg2, <8 x float> %arg3, <8 x float> %arg4) nounwind {
1948-
; CHECK-LABEL: buildvec_vfredusum:
1832+
define <4 x float> @buildvec_vfredusum_slideup(float %start, <8 x float> %arg1, <8 x float> %arg2, <8 x float> %arg3, <8 x float> %arg4) nounwind {
1833+
; CHECK-LABEL: buildvec_vfredusum_slideup:
19491834
; CHECK: # %bb.0:
19501835
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
19511836
; CHECK-NEXT: vfmv.s.f v16, fa0
@@ -1972,8 +1857,118 @@ define <4 x float> @buildvec_vfredusum(float %start, <8 x float> %arg1, <8 x flo
19721857
ret <4 x float> %255
19731858
}
19741859

1975-
define <4 x float> @buildvec_vfredosum(float %start, <8 x float> %arg1, <8 x float> %arg2, <8 x float> %arg3, <8 x float> %arg4) nounwind {
1976-
; CHECK-LABEL: buildvec_vfredosum:
1860+
define <8 x float> @buildvec_vfredusum_slideup_leading_undef(float %start, <8 x float> %arg1, <8 x float> %arg2, <8 x float> %arg3, <8 x float> %arg4) nounwind {
1861+
; CHECK-LABEL: buildvec_vfredusum_slideup_leading_undef:
1862+
; CHECK: # %bb.0:
1863+
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
1864+
; CHECK-NEXT: vfmv.s.f v16, fa0
1865+
; CHECK-NEXT: vfredusum.vs v9, v8, v16
1866+
; CHECK-NEXT: vfredusum.vs v10, v10, v16
1867+
; CHECK-NEXT: vfredusum.vs v11, v12, v16
1868+
; CHECK-NEXT: vfredusum.vs v8, v14, v16
1869+
; CHECK-NEXT: vfmv.f.s fa5, v9
1870+
; CHECK-NEXT: vfmv.f.s fa4, v10
1871+
; CHECK-NEXT: vfmv.f.s fa3, v11
1872+
; CHECK-NEXT: vfslide1up.vf v10, v8, fa3
1873+
; CHECK-NEXT: vfslide1up.vf v8, v10, fa4
1874+
; CHECK-NEXT: vfslide1up.vf v10, v8, fa5
1875+
; CHECK-NEXT: vslideup.vi v8, v10, 4
1876+
; CHECK-NEXT: ret
1877+
%252 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg1)
1878+
%253 = insertelement <8 x float> poison, float %252, i64 4
1879+
%254 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg2)
1880+
%255 = insertelement <8 x float> %253, float %254, i64 5
1881+
%256 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg3)
1882+
%257 = insertelement <8 x float> %255, float %256, i64 6
1883+
%258 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg4)
1884+
%259 = insertelement <8 x float> %257, float %258, i64 7
1885+
ret <8 x float> %259
1886+
}
1887+
1888+
define <8 x float> @buildvec_vfredusum_slideup_trailing_undef(float %start, <8 x float> %arg1, <8 x float> %arg2, <8 x float> %arg3, <8 x float> %arg4) nounwind {
1889+
; CHECK-LABEL: buildvec_vfredusum_slideup_trailing_undef:
1890+
; CHECK: # %bb.0:
1891+
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
1892+
; CHECK-NEXT: vfmv.s.f v16, fa0
1893+
; CHECK-NEXT: vfredusum.vs v9, v8, v16
1894+
; CHECK-NEXT: vfredusum.vs v10, v10, v16
1895+
; CHECK-NEXT: vfredusum.vs v11, v12, v16
1896+
; CHECK-NEXT: vfredusum.vs v8, v14, v16
1897+
; CHECK-NEXT: vfmv.f.s fa5, v9
1898+
; CHECK-NEXT: vfmv.f.s fa4, v10
1899+
; CHECK-NEXT: vfmv.f.s fa3, v11
1900+
; CHECK-NEXT: vfslide1up.vf v10, v8, fa3
1901+
; CHECK-NEXT: vfslide1up.vf v12, v10, fa4
1902+
; CHECK-NEXT: vfslide1up.vf v8, v12, fa5
1903+
; CHECK-NEXT: ret
1904+
%252 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg1)
1905+
%253 = insertelement <8 x float> poison, float %252, i64 0
1906+
%254 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg2)
1907+
%255 = insertelement <8 x float> %253, float %254, i64 1
1908+
%256 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg3)
1909+
%257 = insertelement <8 x float> %255, float %256, i64 2
1910+
%258 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg4)
1911+
%259 = insertelement <8 x float> %257, float %258, i64 3
1912+
ret <8 x float> %259
1913+
}
1914+
1915+
; Negative test case checking if we generate slideup only when all build_vec operands are extraction from the first vector element.
1916+
define <8 x float> @buildvec_vfredusum_slideup_not_extract_first(float %start, <8 x float> %arg1, <8 x float> %arg2, <8 x float> %arg3, <8 x float> %arg4) nounwind {
1917+
; CHECK-LABEL: buildvec_vfredusum_slideup_not_extract_first:
1918+
; CHECK: # %bb.0:
1919+
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
1920+
; CHECK-NEXT: vfmv.s.f v10, fa0
1921+
; CHECK-NEXT: vfredusum.vs v8, v8, v10
1922+
; CHECK-NEXT: vfredusum.vs v9, v12, v10
1923+
; CHECK-NEXT: vfredusum.vs v10, v14, v10
1924+
; CHECK-NEXT: vfmv.f.s fa5, v9
1925+
; CHECK-NEXT: vfmv.f.s fa4, v10
1926+
; CHECK-NEXT: vrgather.vi v10, v8, 0
1927+
; CHECK-NEXT: vfslide1down.vf v8, v10, fa0
1928+
; CHECK-NEXT: vfslide1down.vf v8, v8, fa5
1929+
; CHECK-NEXT: vfslide1down.vf v8, v8, fa4
1930+
; CHECK-NEXT: vslidedown.vi v8, v8, 4
1931+
; CHECK-NEXT: ret
1932+
%252 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg1)
1933+
%253 = insertelement <8 x float> poison, float %252, i64 0
1934+
%255 = insertelement <8 x float> %253, float %start, i64 1
1935+
%256 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg3)
1936+
%257 = insertelement <8 x float> %255, float %256, i64 2
1937+
%258 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg4)
1938+
%259 = insertelement <8 x float> %257, float %258, i64 3
1939+
ret <8 x float> %259
1940+
}
1941+
1942+
define <8 x float> @buildvec_vfredusum_slideup_mid_undef(float %start, <8 x float> %arg1, <8 x float> %arg2, <8 x float> %arg3, <8 x float> %arg4) nounwind {
1943+
; CHECK-LABEL: buildvec_vfredusum_slideup_mid_undef:
1944+
; CHECK: # %bb.0:
1945+
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
1946+
; CHECK-NEXT: vfmv.s.f v16, fa0
1947+
; CHECK-NEXT: vfredusum.vs v9, v8, v16
1948+
; CHECK-NEXT: vfredusum.vs v10, v10, v16
1949+
; CHECK-NEXT: vfredusum.vs v11, v12, v16
1950+
; CHECK-NEXT: vfredusum.vs v8, v14, v16
1951+
; CHECK-NEXT: vfmv.f.s fa5, v9
1952+
; CHECK-NEXT: vfmv.f.s fa4, v10
1953+
; CHECK-NEXT: vfmv.f.s fa3, v11
1954+
; CHECK-NEXT: vfslide1up.vf v10, v8, fa3
1955+
; CHECK-NEXT: vslideup.vi v8, v10, 4
1956+
; CHECK-NEXT: vfslide1up.vf v10, v8, fa4
1957+
; CHECK-NEXT: vfslide1up.vf v8, v10, fa5
1958+
; CHECK-NEXT: ret
1959+
%252 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg1)
1960+
%253 = insertelement <8 x float> poison, float %252, i64 0
1961+
%254 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg2)
1962+
%255 = insertelement <8 x float> %253, float %254, i64 1
1963+
%256 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg3)
1964+
%257 = insertelement <8 x float> %255, float %256, i64 6
1965+
%258 = tail call reassoc float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %arg4)
1966+
%259 = insertelement <8 x float> %257, float %258, i64 7
1967+
ret <8 x float> %259
1968+
}
1969+
1970+
define <4 x float> @buildvec_vfredosum_slideup(float %start, <8 x float> %arg1, <8 x float> %arg2, <8 x float> %arg3, <8 x float> %arg4) nounwind {
1971+
; CHECK-LABEL: buildvec_vfredosum_slideup:
19771972
; CHECK: # %bb.0:
19781973
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
19791974
; CHECK-NEXT: vfmv.s.f v16, fa0

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -3416,8 +3416,8 @@ define <4 x i1> @buildvec_i1_splat(i1 %e1) {
34163416
ret <4 x i1> %v4
34173417
}
34183418

3419-
define <4 x i32> @buildvec_vredsum(<8 x i32> %arg0, <8 x i32> %arg1, <8 x i32> %arg2, <8 x i32> %arg3) nounwind {
3420-
; RV32-LABEL: buildvec_vredsum:
3419+
define <4 x i32> @buildvec_vredsum_slideup(<8 x i32> %arg0, <8 x i32> %arg1, <8 x i32> %arg2, <8 x i32> %arg3) nounwind {
3420+
; RV32-LABEL: buildvec_vredsum_slideup:
34213421
; RV32: # %bb.0:
34223422
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
34233423
; RV32-NEXT: vmv.s.x v16, zero
@@ -3434,7 +3434,7 @@ define <4 x i32> @buildvec_vredsum(<8 x i32> %arg0, <8 x i32> %arg1, <8 x i32> %
34343434
; RV32-NEXT: vslide1up.vx v8, v10, a0
34353435
; RV32-NEXT: ret
34363436
;
3437-
; RV64V-ONLY-LABEL: buildvec_vredsum:
3437+
; RV64V-ONLY-LABEL: buildvec_vredsum_slideup:
34383438
; RV64V-ONLY: # %bb.0:
34393439
; RV64V-ONLY-NEXT: vsetivli zero, 8, e32, m2, ta, ma
34403440
; RV64V-ONLY-NEXT: vmv.s.x v16, zero
@@ -3451,7 +3451,7 @@ define <4 x i32> @buildvec_vredsum(<8 x i32> %arg0, <8 x i32> %arg1, <8 x i32> %
34513451
; RV64V-ONLY-NEXT: vslide1up.vx v8, v10, a0
34523452
; RV64V-ONLY-NEXT: ret
34533453
;
3454-
; RVA22U64-LABEL: buildvec_vredsum:
3454+
; RVA22U64-LABEL: buildvec_vredsum_slideup:
34553455
; RVA22U64: # %bb.0:
34563456
; RVA22U64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
34573457
; RVA22U64-NEXT: vmv.s.x v16, zero
@@ -3472,7 +3472,7 @@ define <4 x i32> @buildvec_vredsum(<8 x i32> %arg0, <8 x i32> %arg1, <8 x i32> %
34723472
; RVA22U64-NEXT: vslide1down.vx v8, v8, a1
34733473
; RVA22U64-NEXT: ret
34743474
;
3475-
; RVA22U64-PACK-LABEL: buildvec_vredsum:
3475+
; RVA22U64-PACK-LABEL: buildvec_vredsum_slideup:
34763476
; RVA22U64-PACK: # %bb.0:
34773477
; RVA22U64-PACK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
34783478
; RVA22U64-PACK-NEXT: vmv.s.x v16, zero
@@ -3491,7 +3491,7 @@ define <4 x i32> @buildvec_vredsum(<8 x i32> %arg0, <8 x i32> %arg1, <8 x i32> %
34913491
; RVA22U64-PACK-NEXT: vslide1down.vx v8, v8, a1
34923492
; RVA22U64-PACK-NEXT: ret
34933493
;
3494-
; RV64ZVE32-LABEL: buildvec_vredsum:
3494+
; RV64ZVE32-LABEL: buildvec_vredsum_slideup:
34953495
; RV64ZVE32: # %bb.0:
34963496
; RV64ZVE32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
34973497
; RV64ZVE32-NEXT: vmv.s.x v16, zero
@@ -3518,8 +3518,8 @@ define <4 x i32> @buildvec_vredsum(<8 x i32> %arg0, <8 x i32> %arg1, <8 x i32> %
35183518
ret <4 x i32> %255
35193519
}
35203520

3521-
define <4 x i32> @buildvec_vredmax(<8 x i32> %arg0, <8 x i32> %arg1, <8 x i32> %arg2, <8 x i32> %arg3) nounwind {
3522-
; RV32-LABEL: buildvec_vredmax:
3521+
define <4 x i32> @buildvec_vredmax_slideup(<8 x i32> %arg0, <8 x i32> %arg1, <8 x i32> %arg2, <8 x i32> %arg3) nounwind {
3522+
; RV32-LABEL: buildvec_vredmax_slideup:
35233523
; RV32: # %bb.0:
35243524
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
35253525
; RV32-NEXT: vredmaxu.vs v8, v8, v8
@@ -3535,7 +3535,7 @@ define <4 x i32> @buildvec_vredmax(<8 x i32> %arg0, <8 x i32> %arg1, <8 x i32> %
35353535
; RV32-NEXT: vslide1up.vx v8, v10, a0
35363536
; RV32-NEXT: ret
35373537
;
3538-
; RV64V-ONLY-LABEL: buildvec_vredmax:
3538+
; RV64V-ONLY-LABEL: buildvec_vredmax_slideup:
35393539
; RV64V-ONLY: # %bb.0:
35403540
; RV64V-ONLY-NEXT: vsetivli zero, 8, e32, m2, ta, ma
35413541
; RV64V-ONLY-NEXT: vredmaxu.vs v8, v8, v8
@@ -3551,7 +3551,7 @@ define <4 x i32> @buildvec_vredmax(<8 x i32> %arg0, <8 x i32> %arg1, <8 x i32> %
35513551
; RV64V-ONLY-NEXT: vslide1up.vx v8, v10, a0
35523552
; RV64V-ONLY-NEXT: ret
35533553
;
3554-
; RVA22U64-LABEL: buildvec_vredmax:
3554+
; RVA22U64-LABEL: buildvec_vredmax_slideup:
35553555
; RVA22U64: # %bb.0:
35563556
; RVA22U64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
35573557
; RVA22U64-NEXT: vredmaxu.vs v8, v8, v8
@@ -3571,7 +3571,7 @@ define <4 x i32> @buildvec_vredmax(<8 x i32> %arg0, <8 x i32> %arg1, <8 x i32> %
35713571
; RVA22U64-NEXT: vslide1down.vx v8, v8, a1
35723572
; RVA22U64-NEXT: ret
35733573
;
3574-
; RVA22U64-PACK-LABEL: buildvec_vredmax:
3574+
; RVA22U64-PACK-LABEL: buildvec_vredmax_slideup:
35753575
; RVA22U64-PACK: # %bb.0:
35763576
; RVA22U64-PACK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
35773577
; RVA22U64-PACK-NEXT: vredmaxu.vs v8, v8, v8
@@ -3589,7 +3589,7 @@ define <4 x i32> @buildvec_vredmax(<8 x i32> %arg0, <8 x i32> %arg1, <8 x i32> %
35893589
; RVA22U64-PACK-NEXT: vslide1down.vx v8, v8, a1
35903590
; RVA22U64-PACK-NEXT: ret
35913591
;
3592-
; RV64ZVE32-LABEL: buildvec_vredmax:
3592+
; RV64ZVE32-LABEL: buildvec_vredmax_slideup:
35933593
; RV64ZVE32: # %bb.0:
35943594
; RV64ZVE32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
35953595
; RV64ZVE32-NEXT: vredmaxu.vs v8, v8, v8

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