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[AMDGPU] add tests for Change FLAT SADDR to VADDR form in moveToVALU. NFC. (#149392)
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‎llvm/lib/Target/AMDGPU/FLATInstructions.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -200,6 +200,7 @@ class VFLAT_Real <bits<8> op, FLAT_Pseudo ps, string opName = ps.Mnemonic> :
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let Inst{95-72} = !if(ps.has_offset, offset, ?);
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}
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// TODO: Rename to FlatSaddrTable, it now handles both global and flat GVS addressing mode.
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class GlobalSaddrTable <bit is_saddr, string Name = ""> {
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bit IsSaddr = is_saddr;
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string SaddrOp = Name;

‎llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu-flat.mir

Lines changed: 357 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,357 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=si-fix-sgpr-copies -o - %s | FileCheck --check-prefix=GCN %s
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---
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name: flat_load_saddr_to_valu
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tracksRegLiveness: true
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body: |
8+
; GCN-LABEL: name: flat_load_saddr_to_valu
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; GCN: bb.0:
10+
; GCN-NEXT: successors: %bb.1(0x80000000)
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; GCN-NEXT: liveins: $vgpr0_vgpr1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.1:
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; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; GCN-NEXT: {{ $}}
18+
; GCN-NEXT: [[PHI:%[0-9]+]]:vreg_64_align2 = PHI [[COPY]], %bb.0, %7, %bb.1
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; GCN-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[PHI]], 0, 0, implicit $exec, implicit $flat_scr
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; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
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; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
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; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
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; GCN-NEXT: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
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; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
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; GCN-NEXT: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], 0, implicit $exec
26+
; GCN-NEXT: [[COPY3:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]], implicit $exec
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; GCN-NEXT: $vcc_lo = S_AND_B32 $exec_lo, [[V_CMP_NE_U64_e64_]], implicit-def $scc
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; GCN-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc_lo
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.2:
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; GCN-NEXT: S_ENDPGM 0
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bb.0:
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liveins: $vgpr0_vgpr1
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%0:sreg_64 = COPY $vgpr0_vgpr1
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bb.1:
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%1:sreg_64_xexec_xnull = PHI %0, %bb.0, %2, %bb.1
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%3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%4:vgpr_32 = FLAT_LOAD_DWORD_SADDR %1, %3, 0, 0, implicit $exec, implicit $flat_scr
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%2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
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S_CMP_LG_U64 %2, 0, implicit-def $scc
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S_CBRANCH_SCC1 %bb.1, implicit $scc
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bb.2:
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S_ENDPGM 0
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...
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48+
---
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name: flat_load_saddr_to_valu_non_zero_vaddr
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tracksRegLiveness: true
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body: |
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; GCN-LABEL: name: flat_load_saddr_to_valu_non_zero_vaddr
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; GCN: bb.0:
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; GCN-NEXT: successors: %bb.1(0x80000000)
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; GCN-NEXT: liveins: $vgpr0_vgpr1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.1:
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; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[PHI:%[0-9]+]]:vreg_64_align2 = PHI [[COPY]], %bb.0, %7, %bb.1
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; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
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; GCN-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub0, implicit $exec
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; GCN-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub1, implicit $exec
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; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
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; GCN-NEXT: [[FLAT_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD_SADDR [[REG_SEQUENCE]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec, implicit $flat_scr
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; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
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; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
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; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
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; GCN-NEXT: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
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; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
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; GCN-NEXT: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE1]], 0, implicit $exec
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; GCN-NEXT: [[COPY3:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE1]], implicit $exec
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; GCN-NEXT: $vcc_lo = S_AND_B32 $exec_lo, [[V_CMP_NE_U64_e64_]], implicit-def $scc
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; GCN-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc_lo
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.2:
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; GCN-NEXT: S_ENDPGM 0
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bb.0:
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liveins: $vgpr0_vgpr1
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%0:sreg_64 = COPY $vgpr0_vgpr1
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bb.1:
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%1:sreg_64_xexec_xnull = PHI %0, %bb.0, %2, %bb.1
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%3:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
87+
%4:vgpr_32 = FLAT_LOAD_DWORD_SADDR %1, %3, 0, 0, implicit $exec, implicit $flat_scr
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%2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
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S_CMP_LG_U64 %2, 0, implicit-def $scc
90+
S_CBRANCH_SCC1 %bb.1, implicit $scc
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bb.2:
93+
S_ENDPGM 0
94+
...
95+
96+
97+
---
98+
name: flat_load_saddr_to_valu_undef_vaddr
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tracksRegLiveness: true
100+
body: |
101+
; GCN-LABEL: name: flat_load_saddr_to_valu_undef_vaddr
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; GCN: bb.0:
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; GCN-NEXT: successors: %bb.1(0x80000000)
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; GCN-NEXT: liveins: $vgpr0_vgpr1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.1:
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; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[PHI:%[0-9]+]]:vreg_64_align2 = PHI [[COPY]], %bb.0, %7, %bb.1
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; GCN-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub0, implicit $exec
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; GCN-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub1, implicit $exec
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; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
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; GCN-NEXT: [[FLAT_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD_SADDR [[REG_SEQUENCE]], undef %4:vgpr_32, 0, 0, implicit $exec, implicit $flat_scr
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; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
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; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
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; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
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; GCN-NEXT: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
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; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
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; GCN-NEXT: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE1]], 0, implicit $exec
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; GCN-NEXT: [[COPY3:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE1]], implicit $exec
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; GCN-NEXT: $vcc_lo = S_AND_B32 $exec_lo, [[V_CMP_NE_U64_e64_]], implicit-def $scc
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; GCN-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc_lo
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.2:
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; GCN-NEXT: S_ENDPGM 0
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bb.0:
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liveins: $vgpr0_vgpr1
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%0:sreg_64 = COPY $vgpr0_vgpr1
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bb.1:
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%1:sreg_64_xexec_xnull = PHI %0, %bb.0, %2, %bb.1
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%4:vgpr_32 = FLAT_LOAD_DWORD_SADDR %1, undef %3:vgpr_32, 0, 0, implicit $exec, implicit $flat_scr
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%2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
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S_CMP_LG_U64 %2, 0, implicit-def $scc
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S_CBRANCH_SCC1 %bb.1, implicit $scc
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bb.2:
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S_ENDPGM 0
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...
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---
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name: flat_store_saddr_to_valu
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tracksRegLiveness: true
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body: |
147+
; GCN-LABEL: name: flat_store_saddr_to_valu
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; GCN: bb.0:
149+
; GCN-NEXT: successors: %bb.1(0x80000000)
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; GCN-NEXT: liveins: $vgpr0_vgpr1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.1:
155+
; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[PHI:%[0-9]+]]:vreg_64_align2 = PHI [[COPY]], %bb.0, %7, %bb.1
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; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GCN-NEXT: FLAT_STORE_DWORD [[PHI]], [[DEF]], 0, 0, implicit $exec, implicit $flat_scr
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; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
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; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
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; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
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; GCN-NEXT: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
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; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
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; GCN-NEXT: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], 0, implicit $exec
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; GCN-NEXT: [[COPY3:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]], implicit $exec
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; GCN-NEXT: $vcc_lo = S_AND_B32 $exec_lo, [[V_CMP_NE_U64_e64_]], implicit-def $scc
168+
; GCN-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc_lo
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; GCN-NEXT: {{ $}}
170+
; GCN-NEXT: bb.2:
171+
; GCN-NEXT: S_ENDPGM 0
172+
bb.0:
173+
liveins: $vgpr0_vgpr1
174+
%0:sreg_64 = COPY $vgpr0_vgpr1
175+
176+
bb.1:
177+
%1:sreg_64_xexec_xnull = PHI %0, %bb.0, %2, %bb.1
178+
%3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
179+
%4:vgpr_32 = IMPLICIT_DEF
180+
FLAT_STORE_DWORD_SADDR %3, %4, %1, 0, 0, implicit $exec, implicit $flat_scr
181+
%2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
182+
S_CMP_LG_U64 %2, 0, implicit-def $scc
183+
S_CBRANCH_SCC1 %bb.1, implicit $scc
184+
185+
bb.2:
186+
S_ENDPGM 0
187+
...
188+
189+
---
190+
name: flat_atomic_noret_saddr_to_valu
191+
tracksRegLiveness: true
192+
body: |
193+
; GCN-LABEL: name: flat_atomic_noret_saddr_to_valu
194+
; GCN: bb.0:
195+
; GCN-NEXT: successors: %bb.1(0x80000000)
196+
; GCN-NEXT: liveins: $vgpr0_vgpr1
197+
; GCN-NEXT: {{ $}}
198+
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
199+
; GCN-NEXT: {{ $}}
200+
; GCN-NEXT: bb.1:
201+
; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
202+
; GCN-NEXT: {{ $}}
203+
; GCN-NEXT: [[PHI:%[0-9]+]]:vreg_64_align2 = PHI [[COPY]], %bb.0, %6, %bb.1
204+
; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
205+
; GCN-NEXT: FLAT_ATOMIC_ADD [[PHI]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec, implicit $flat_scr
206+
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
207+
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
208+
; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
209+
; GCN-NEXT: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
210+
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
211+
; GCN-NEXT: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], 0, implicit $exec
212+
; GCN-NEXT: [[COPY3:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]], implicit $exec
213+
; GCN-NEXT: $vcc_lo = S_AND_B32 $exec_lo, [[V_CMP_NE_U64_e64_]], implicit-def $scc
214+
; GCN-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc_lo
215+
; GCN-NEXT: {{ $}}
216+
; GCN-NEXT: bb.2:
217+
; GCN-NEXT: S_ENDPGM 0
218+
bb.0:
219+
liveins: $vgpr0_vgpr1
220+
%0:sreg_64 = COPY $vgpr0_vgpr1
221+
222+
bb.1:
223+
%1:sreg_64_xexec_xnull = PHI %0, %bb.0, %2, %bb.1
224+
%3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
225+
FLAT_ATOMIC_ADD_SADDR %3, %3, %1, 0, 0, implicit $exec, implicit $flat_scr
226+
%2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
227+
S_CMP_LG_U64 %2, 0, implicit-def $scc
228+
S_CBRANCH_SCC1 %bb.1, implicit $scc
229+
230+
bb.2:
231+
S_ENDPGM 0
232+
...
233+
234+
---
235+
name: flat_atomic_rtn_saddr_to_valu
236+
tracksRegLiveness: true
237+
body: |
238+
; GCN-LABEL: name: flat_atomic_rtn_saddr_to_valu
239+
; GCN: bb.0:
240+
; GCN-NEXT: successors: %bb.1(0x80000000)
241+
; GCN-NEXT: liveins: $vgpr0_vgpr1
242+
; GCN-NEXT: {{ $}}
243+
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
244+
; GCN-NEXT: {{ $}}
245+
; GCN-NEXT: bb.1:
246+
; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
247+
; GCN-NEXT: {{ $}}
248+
; GCN-NEXT: [[PHI:%[0-9]+]]:vreg_64_align2 = PHI [[COPY]], %bb.0, %7, %bb.1
249+
; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
250+
; GCN-NEXT: [[FLAT_ATOMIC_ADD_RTN:%[0-9]+]]:vgpr_32 = FLAT_ATOMIC_ADD_RTN [[PHI]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec, implicit $flat_scr
251+
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
252+
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
253+
; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
254+
; GCN-NEXT: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
255+
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
256+
; GCN-NEXT: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], 0, implicit $exec
257+
; GCN-NEXT: [[COPY3:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]], implicit $exec
258+
; GCN-NEXT: $vcc_lo = S_AND_B32 $exec_lo, [[V_CMP_NE_U64_e64_]], implicit-def $scc
259+
; GCN-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc_lo
260+
; GCN-NEXT: {{ $}}
261+
; GCN-NEXT: bb.2:
262+
; GCN-NEXT: S_ENDPGM 0
263+
bb.0:
264+
liveins: $vgpr0_vgpr1
265+
%0:sreg_64 = COPY $vgpr0_vgpr1
266+
267+
bb.1:
268+
%1:sreg_64_xexec_xnull = PHI %0, %bb.0, %2, %bb.1
269+
%3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
270+
%4:vgpr_32 = FLAT_ATOMIC_ADD_SADDR_RTN %3, %3, %1, 0, 0, implicit $exec, implicit $flat_scr
271+
%2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
272+
S_CMP_LG_U64 %2, 0, implicit-def $scc
273+
S_CBRANCH_SCC1 %bb.1, implicit $scc
274+
275+
bb.2:
276+
S_ENDPGM 0
277+
...
278+
279+
---
280+
name: scratch_load_saddr_to_valu
281+
tracksRegLiveness: true
282+
body: |
283+
; GCN-LABEL: name: scratch_load_saddr_to_valu
284+
; GCN: bb.0:
285+
; GCN-NEXT: successors: %bb.1(0x80000000)
286+
; GCN-NEXT: liveins: $vgpr0
287+
; GCN-NEXT: {{ $}}
288+
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
289+
; GCN-NEXT: {{ $}}
290+
; GCN-NEXT: bb.1:
291+
; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
292+
; GCN-NEXT: {{ $}}
293+
; GCN-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, %6, %bb.1
294+
; GCN-NEXT: [[SCRATCH_LOAD_DWORD:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_DWORD [[PHI]], 0, 0, implicit $exec, implicit $flat_scr
295+
; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[PHI]], 1, implicit $exec
296+
; GCN-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 [[V_AND_B32_e64_]], 0, implicit $exec
297+
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[V_AND_B32_e64_]], implicit $exec
298+
; GCN-NEXT: $vcc_lo = S_AND_B32 $exec_lo, [[V_CMP_NE_U32_e64_]], implicit-def $scc
299+
; GCN-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc_lo
300+
; GCN-NEXT: {{ $}}
301+
; GCN-NEXT: bb.2:
302+
; GCN-NEXT: S_ENDPGM 0
303+
bb.0:
304+
liveins: $vgpr0
305+
%0:sgpr_32 = COPY $vgpr0
306+
307+
bb.1:
308+
%1:sgpr_32 = PHI %0, %bb.0, %2, %bb.1
309+
%4:vgpr_32 = SCRATCH_LOAD_DWORD_SADDR %1, 0, 0, implicit $exec, implicit $flat_scr
310+
%2:sgpr_32 = S_AND_B32 %1, 1, implicit-def $scc
311+
S_CMP_LG_U32 %2, 0, implicit-def $scc
312+
S_CBRANCH_SCC1 %bb.1, implicit $scc
313+
314+
bb.2:
315+
S_ENDPGM 0
316+
...
317+
318+
---
319+
name: scratch_store_saddr_to_valu
320+
tracksRegLiveness: true
321+
body: |
322+
; GCN-LABEL: name: scratch_store_saddr_to_valu
323+
; GCN: bb.0:
324+
; GCN-NEXT: successors: %bb.1(0x80000000)
325+
; GCN-NEXT: liveins: $vgpr0
326+
; GCN-NEXT: {{ $}}
327+
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
328+
; GCN-NEXT: {{ $}}
329+
; GCN-NEXT: bb.1:
330+
; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
331+
; GCN-NEXT: {{ $}}
332+
; GCN-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, %6, %bb.1
333+
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
334+
; GCN-NEXT: SCRATCH_STORE_DWORD [[DEF]], [[PHI]], 0, 0, implicit $exec, implicit $flat_scr
335+
; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[PHI]], 1, implicit $exec
336+
; GCN-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 [[V_AND_B32_e64_]], 0, implicit $exec
337+
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[V_AND_B32_e64_]], implicit $exec
338+
; GCN-NEXT: $vcc_lo = S_AND_B32 $exec_lo, [[V_CMP_NE_U32_e64_]], implicit-def $scc
339+
; GCN-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc_lo
340+
; GCN-NEXT: {{ $}}
341+
; GCN-NEXT: bb.2:
342+
; GCN-NEXT: S_ENDPGM 0
343+
bb.0:
344+
liveins: $vgpr0
345+
%0:sgpr_32 = COPY $vgpr0
346+
347+
bb.1:
348+
%1:sgpr_32 = PHI %0, %bb.0, %2, %bb.1
349+
%4:vgpr_32 = IMPLICIT_DEF
350+
SCRATCH_STORE_DWORD_SADDR %4, %1, 0, 0, implicit $exec, implicit $flat_scr
351+
%2:sgpr_32 = S_AND_B32 %1, 1, implicit-def $scc
352+
S_CMP_LG_U32 %2, 0, implicit-def $scc
353+
S_CBRANCH_SCC1 %bb.1, implicit $scc
354+
355+
bb.2:
356+
S_ENDPGM 0
357+
...

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