Skip to content

Commit 429910e

Browse files
added comments to responde to review
Signed-off-by: Alexandre Eichenberger <[email protected]>
1 parent 23b37c5 commit 429910e

File tree

1 file changed

+3
-0
lines changed

1 file changed

+3
-0
lines changed

mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1351,6 +1351,9 @@ def MemRef_PrefetchOp : MemRef_Op<"prefetch"> {
13511351
instruction cache.
13521352
}];
13531353

1354+
// The memref argument is labeled with a MemWrite side effect to enforce a
1355+
// relative ordering of the prefetch and other memory operations targeting
1356+
// that memory stream.
13541357
let arguments = (ins Arg<AnyMemRef, "prefetch address", [MemWrite]> :$memref,
13551358
Variadic<Index>:$indices,
13561359
BoolAttr:$isWrite,

0 commit comments

Comments
 (0)