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[RISCV] Add option to disable ASM compress.
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2 files changed

+47
-1
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2 files changed

+47
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llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3273,9 +3273,17 @@ bool RISCVAsmParser::parseDirectiveVariantCC() {
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return false;
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}
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static cl::opt<bool> RVDisableInlineAsmCompress(
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"riscv-disable-inline-asm-compress",
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cl::desc("disable compressing inline-asm instructions to their compress "
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"counterpart."),
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cl::init(false), cl::Hidden);
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void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) {
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MCInst CInst;
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bool Res = RISCVRVC::compress(CInst, Inst, getSTI());
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bool Res = false;
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if (!RVDisableInlineAsmCompress)
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Res = RISCVRVC::compress(CInst, Inst, getSTI());
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if (Res)
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++RISCVNumInstrsCompressed;
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S.emitInstruction((Res ? CInst : Inst), getSTI());
Lines changed: 38 additions & 0 deletions
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@@ -0,0 +1,38 @@
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; NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --llvm-mc-binary bin/llvm-mc --version 5
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# RUN: llvm-mc -triple riscv32 -mattr=+c -assemble -riscv-no-aliases -show-encoding < %s | FileCheck %s --check-prefix=ENABLED
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# RUN: llvm-mc -triple riscv32 -mattr=+c -assemble -riscv-no-aliases -show-encoding -riscv-disable-inline-asm-compress < %s | FileCheck %s --check-prefix=DISABLED
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addi sp, sp, -16
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// ENABLED: c.addi sp, -16 # encoding: [0x41,0x11]
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// DISABLED: addi sp, sp, -16 # encoding: [0x13,0x01,0x01,0xff]
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sw ra, 12(sp)
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// ENABLED: c.swsp ra, 12(sp) # encoding: [0x06,0xc6]
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// DISABLED: sw ra, 12(sp) # encoding: [0x23,0x26,0x11,0x00]
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sw s0, 8(sp)
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// ENABLED: c.swsp s0, 8(sp) # encoding: [0x22,0xc4]
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// DISABLED: sw s0, 8(sp) # encoding: [0x23,0x24,0x81,0x00]
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addi s0, sp, 16
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// ENABLED: c.addi4spn s0, sp, 16 # encoding: [0x00,0x08]
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// DISABLED: addi s0, sp, 16 # encoding: [0x13,0x04,0x01,0x01]
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li a0, 0
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// ENABLED: c.li a0, 0 # encoding: [0x01,0x45]
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// DISABLED: addi a0, zero, 0 # encoding: [0x13,0x05,0x00,0x00]
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sw a0, -12(s0)
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// ENABLED: sw a0, -12(s0) # encoding: [0x23,0x2a,0xa4,0xfe]
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// DISABLED: sw a0, -12(s0) # encoding: [0x23,0x2a,0xa4,0xfe]
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lw ra, 12(sp)
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// ENABLED: c.lwsp ra, 12(sp) # encoding: [0xb2,0x40]
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// DISABLED: lw ra, 12(sp) # encoding: [0x83,0x20,0xc1,0x00]
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lw s0, 8(sp)
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// ENABLED: c.lwsp s0, 8(sp) # encoding: [0x22,0x44]
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// DISABLED: lw s0, 8(sp) # encoding: [0x03,0x24,0x81,0x00]
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addi sp, sp, 16
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// ENABLED: c.addi sp, 16 # encoding: [0x41,0x01]
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// DISABLED: addi sp, sp, 16 # encoding: [0x13,0x01,0x01,0x01]
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ret
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// ENABLED: c.jr ra # encoding: [0x82,0x80]
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// DISABLED: jalr zero, 0(ra) # encoding: [0x67,0x80,0x00,0x00]
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