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[NFC] using isUndef() instead of getOpcode() == ISD::UNDEF
1 parent 7eaaa4e commit 42bae32

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3 files changed

+18
-18
lines changed

3 files changed

+18
-18
lines changed

llvm/include/llvm/CodeGen/SelectionDAG.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -873,7 +873,7 @@ class SelectionDAG {
873873
/// for integers, a type wider than) VT's element type.
874874
SDValue getSplatBuildVector(EVT VT, const SDLoc &DL, SDValue Op) {
875875
// VerifySDNode (via InsertNode) checks BUILD_VECTOR later.
876-
if (Op.getOpcode() == ISD::UNDEF) {
876+
if (Op.isUndef()) {
877877
assert((VT.getVectorElementType() == Op.getValueType() ||
878878
(VT.isInteger() &&
879879
VT.getVectorElementType().bitsLE(Op.getValueType()))) &&
@@ -889,7 +889,7 @@ class SelectionDAG {
889889
// Return a splat ISD::SPLAT_VECTOR node, consisting of Op splatted to all
890890
// elements.
891891
SDValue getSplatVector(EVT VT, const SDLoc &DL, SDValue Op) {
892-
if (Op.getOpcode() == ISD::UNDEF) {
892+
if (Op.isUndef()) {
893893
assert((VT.getVectorElementType() == Op.getValueType() ||
894894
(VT.isInteger() &&
895895
VT.getVectorElementType().bitsLE(Op.getValueType()))) &&

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -16145,7 +16145,7 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) {
1614516145
// also recursively replace t184 by t150.
1614616146
SDValue MaybePoisonOperand = N->getOperand(0).getOperand(OpNo);
1614716147
// Don't replace every single UNDEF everywhere with frozen UNDEF, though.
16148-
if (MaybePoisonOperand.getOpcode() == ISD::UNDEF)
16148+
if (MaybePoisonOperand.isUndef())
1614916149
continue;
1615016150
// First, freeze each offending operand.
1615116151
SDValue FrozenMaybePoisonOperand = DAG.getFreeze(MaybePoisonOperand);
@@ -16173,7 +16173,7 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) {
1617316173
SmallVector<SDValue> Ops(N0->ops());
1617416174
// Special-handle ISD::UNDEF, each single one of them can be it's own thing.
1617516175
for (SDValue &Op : Ops) {
16176-
if (Op.getOpcode() == ISD::UNDEF)
16176+
if (Op.isUndef())
1617716177
Op = DAG.getFreeze(Op);
1617816178
}
1617916179

@@ -24289,7 +24289,7 @@ static SDValue combineConcatVectorOfScalars(SDNode *N, SelectionDAG &DAG) {
2428924289
if (ISD::BITCAST == Op.getOpcode() &&
2429024290
!Op.getOperand(0).getValueType().isVector())
2429124291
Ops.push_back(Op.getOperand(0));
24292-
else if (ISD::UNDEF == Op.getOpcode())
24292+
else if (Op.isUndef())
2429324293
Ops.push_back(DAG.getNode(ISD::UNDEF, DL, SVT));
2429424294
else
2429524295
return SDValue();
@@ -24684,7 +24684,7 @@ SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
2468424684
// fold (concat_vectors (BUILD_VECTOR A, B, ...), (BUILD_VECTOR C, D, ...))
2468524685
// -> (BUILD_VECTOR A, B, ..., C, D, ...)
2468624686
auto IsBuildVectorOrUndef = [](const SDValue &Op) {
24687-
return ISD::UNDEF == Op.getOpcode() || ISD::BUILD_VECTOR == Op.getOpcode();
24687+
return Op.isUndef() || ISD::BUILD_VECTOR == Op.getOpcode();
2468824688
};
2468924689
if (llvm::all_of(N->ops(), IsBuildVectorOrUndef)) {
2469024690
SmallVector<SDValue, 8> Opnds;
@@ -24708,7 +24708,7 @@ SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
2470824708
EVT OpVT = Op.getValueType();
2470924709
unsigned NumElts = OpVT.getVectorNumElements();
2471024710

24711-
if (ISD::UNDEF == Op.getOpcode())
24711+
if (Op.isUndef())
2471224712
Opnds.append(NumElts, DAG.getUNDEF(MinVT));
2471324713

2471424714
if (ISD::BUILD_VECTOR == Op.getOpcode()) {

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -6314,7 +6314,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
63146314
Flags.setNonNeg(N1->getFlags().hasNonNeg());
63156315
return getNode(OpOpcode, DL, VT, N1.getOperand(0), Flags);
63166316
}
6317-
if (OpOpcode == ISD::UNDEF)
6317+
if (N1.isUndef())
63186318
// sext(undef) = 0, because the top bits will all be the same.
63196319
return getConstant(0, DL, VT);
63206320
break;
@@ -6334,7 +6334,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
63346334
Flags.setNonNeg(N1->getFlags().hasNonNeg());
63356335
return getNode(ISD::ZERO_EXTEND, DL, VT, N1.getOperand(0), Flags);
63366336
}
6337-
if (OpOpcode == ISD::UNDEF)
6337+
if (N1.isUndef())
63386338
// zext(undef) = 0, because the top bits will be zero.
63396339
return getConstant(0, DL, VT);
63406340

@@ -6376,7 +6376,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
63766376
// (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x)
63776377
return getNode(OpOpcode, DL, VT, N1.getOperand(0), Flags);
63786378
}
6379-
if (OpOpcode == ISD::UNDEF)
6379+
if (N1.isUndef())
63806380
return getUNDEF(VT);
63816381

63826382
// (ext (trunc x)) -> x
@@ -6411,7 +6411,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
64116411
return getNode(ISD::TRUNCATE, DL, VT, N1.getOperand(0));
64126412
return N1.getOperand(0);
64136413
}
6414-
if (OpOpcode == ISD::UNDEF)
6414+
if (N1.isUndef())
64156415
return getUNDEF(VT);
64166416
if (OpOpcode == ISD::VSCALE && !NewNodesMustHaveLegalTypes)
64176417
return getVScale(DL, VT,
@@ -6429,22 +6429,22 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
64296429
break;
64306430
case ISD::ABS:
64316431
assert(VT.isInteger() && VT == N1.getValueType() && "Invalid ABS!");
6432-
if (OpOpcode == ISD::UNDEF)
6432+
if (N1.isUndef())
64336433
return getConstant(0, DL, VT);
64346434
break;
64356435
case ISD::BSWAP:
64366436
assert(VT.isInteger() && VT == N1.getValueType() && "Invalid BSWAP!");
64376437
assert((VT.getScalarSizeInBits() % 16 == 0) &&
64386438
"BSWAP types must be a multiple of 16 bits!");
6439-
if (OpOpcode == ISD::UNDEF)
6439+
if (N1.isUndef())
64406440
return getUNDEF(VT);
64416441
// bswap(bswap(X)) -> X.
64426442
if (OpOpcode == ISD::BSWAP)
64436443
return N1.getOperand(0);
64446444
break;
64456445
case ISD::BITREVERSE:
64466446
assert(VT.isInteger() && VT == N1.getValueType() && "Invalid BITREVERSE!");
6447-
if (OpOpcode == ISD::UNDEF)
6447+
if (N1.isUndef())
64486448
return getUNDEF(VT);
64496449
break;
64506450
case ISD::BITCAST:
@@ -6453,7 +6453,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
64536453
if (VT == N1.getValueType()) return N1; // noop conversion.
64546454
if (OpOpcode == ISD::BITCAST) // bitconv(bitconv(x)) -> bitconv(x)
64556455
return getNode(ISD::BITCAST, DL, VT, N1.getOperand(0));
6456-
if (OpOpcode == ISD::UNDEF)
6456+
if (N1.isUndef())
64576457
return getUNDEF(VT);
64586458
break;
64596459
case ISD::SCALAR_TO_VECTOR:
@@ -6463,7 +6463,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
64636463
N1.getValueType().isInteger() &&
64646464
VT.getVectorElementType().bitsLE(N1.getValueType()))) &&
64656465
"Illegal SCALAR_TO_VECTOR node!");
6466-
if (OpOpcode == ISD::UNDEF)
6466+
if (N1.isUndef())
64676467
return getUNDEF(VT);
64686468
// scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined.
64696469
if (OpOpcode == ISD::EXTRACT_VECTOR_ELT &&
@@ -6474,7 +6474,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
64746474
break;
64756475
case ISD::FNEG:
64766476
// Negation of an unknown bag of bits is still completely undefined.
6477-
if (OpOpcode == ISD::UNDEF)
6477+
if (N1.isUndef())
64786478
return getUNDEF(VT);
64796479

64806480
if (OpOpcode == ISD::FNEG) // --X -> X
@@ -13380,7 +13380,7 @@ void BuildVectorSDNode::recastRawBits(bool IsLittleEndian,
1338013380
bool BuildVectorSDNode::isConstant() const {
1338113381
for (const SDValue &Op : op_values()) {
1338213382
unsigned Opc = Op.getOpcode();
13383-
if (Opc != ISD::UNDEF && Opc != ISD::Constant && Opc != ISD::ConstantFP)
13383+
if (!Op.isUndef() && Opc != ISD::Constant && Opc != ISD::ConstantFP)
1338413384
return false;
1338513385
}
1338613386
return true;

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