[Hexagon] Improve QFP Optimizer

This patch enhances HexagonQFPOptimizer in multiple ways:

1. Refactor the code for better readability and maintainability.

2. Optimize vabs,vneg and vilog2 converts

   The three instruction mentioned can be optimized like below:

  ```v1.sf = v0.qf32
    v2.qf = vneg v1.sf```

  to

  ```v2.qf = vneg v0.qf32```

  This optimization eliminates one conversion and is applicable
  to both qf32 and qf16 types.

3. Enable vsub fusion with mixed arguments
   Previously, QFPOptimizer did not fuse partial qfloat operands with vsub.
   This update allows selective use of vsub_hf_mix, vsub_sf_mix, vsub_qf16_mix,
   and vsub_qf32_mix when appropriate. It also enables QFP simplifications
   involving vector pair subregisters.

   Example scenario in a machine basic block targeting Hexagon:
   ```v1.qf32 = ... // result of a vadd
      v2.sf   = v1.qf32
      v3.qf32 = vmpy(v2.sf, v2.sf)```

4. Remove redundant conversions
   Under certain conditions, we previously bailed out before removing qf-to-sf/hf conversions.
   This patch removes that bailout, enabling more aggressive elimination of unnecessary conversions.

5. Don't optimize equals feeding into multiply:
   Removing converts feeding into multiply loses precision.
   This patch avoids optimizing multiplies along with giving the
   users an option to enable this by a flag.

Patch By: Fateme Hosseini

Co-authored-by: Kaushik Kulkarni <[email protected]>
Co-authored-by: Santanu Das <[email protected]>

Author: 3 people

llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp

@@ -4753,6 +4753,19 @@ bool HexagonInstrInfo::getBundleNoShuf(const MachineInstr &MIB) const {
   return (Operand.isImm() && (Operand.getImm() & memShufDisabledMask) != 0);
 }
 
+bool HexagonInstrInfo::isQFPMul(const MachineInstr *MI) const {
+  return (MI->getOpcode() == Hexagon::V6_vmpy_qf16_hf ||
+          MI->getOpcode() == Hexagon::V6_vmpy_qf16_mix_hf ||
+          MI->getOpcode() == Hexagon::V6_vmpy_qf32_hf ||
+          MI->getOpcode() == Hexagon::V6_vmpy_qf32_mix_hf ||
+          MI->getOpcode() == Hexagon::V6_vmpy_qf32_sf ||
+          MI->getOpcode() == Hexagon::V6_vmpy_qf16_mix_hf ||
+          MI->getOpcode() == Hexagon::V6_vmpy_qf16 ||
+          MI->getOpcode() == Hexagon::V6_vmpy_qf32_mix_hf ||
+          MI->getOpcode() == Hexagon::V6_vmpy_qf32_qf16 ||
+          MI->getOpcode() == Hexagon::V6_vmpy_qf32);
+}
+
 // Addressing mode relations.
 short HexagonInstrInfo::changeAddrMode_abs_io(short Opc) const {
   return Opc >= 0 ? Hexagon::changeAddrMode_abs_io(Opc) : Opc;

llvm/lib/Target/Hexagon/HexagonInstrInfo.h

@@ -532,6 +532,7 @@ class HexagonInstrInfo : public HexagonGenInstrInfo {
   }
 
   MCInst getNop() const override;
+  bool isQFPMul(const MachineInstr *MF) const;
 };
 
 /// \brief Create RegSubRegPair from a register MachineOperand

llvm/lib/Target/Hexagon/HexagonQFPOptimizer.cpp

@@ -58,7 +58,7 @@
 // are PHI inst.
 //
 //===----------------------------------------------------------------------===//
-#include <unordered_set>
+
 #define HEXAGON_QFP_OPTIMIZER "QFP optimizer pass"
 
 #include "Hexagon.h"
@@ -86,6 +86,10 @@ using namespace llvm;
 cl::opt<bool>
     DisableQFOptimizer("disable-qfp-opt", cl::init(false),
                        cl::desc("Disable optimization of Qfloat operations."));
+cl::opt<bool>
+    DisableQFOptForMul("disable-qfp-opt-mul", cl::init(true),
+     cl::desc(
+  "Disable optimization of Qfloat operations for multiply."));
 
 namespace {
 const std::map<unsigned short, unsigned short> QFPInstMap{
@@ -101,96 +105,135 @@ const std::map<unsigned short, unsigned short> QFPInstMap{
     {Hexagon::V6_vmpy_qf16_mix_hf, Hexagon::V6_vmpy_qf16},
     {Hexagon::V6_vmpy_qf32_hf, Hexagon::V6_vmpy_qf32_mix_hf},
     {Hexagon::V6_vmpy_qf32_mix_hf, Hexagon::V6_vmpy_qf32_qf16},
-    {Hexagon::V6_vmpy_qf32_sf, Hexagon::V6_vmpy_qf32}};
+    {Hexagon::V6_vmpy_qf32_sf, Hexagon::V6_vmpy_qf32},
+    {Hexagon::V6_vilog2_sf, Hexagon::V6_vilog2_qf32},
+    {Hexagon::V6_vilog2_hf, Hexagon::V6_vilog2_qf16},
+    {Hexagon::V6_vabs_qf32_sf, Hexagon::V6_vabs_qf32_qf32},
+    {Hexagon::V6_vabs_qf16_hf, Hexagon::V6_vabs_qf16_qf16},
+    {Hexagon::V6_vneg_qf32_sf, Hexagon::V6_vneg_qf32_qf32},
+    {Hexagon::V6_vneg_qf16_hf, Hexagon::V6_vneg_qf16_qf16}};
 } // namespace
 
-namespace {
+namespace llvm {
+FunctionPass *createHexagonQFPOptimizer();
+void initializeHexagonQFPOptimizerPass(PassRegistry &);
+} // namespace llvm
 
+namespace {
 struct HexagonQFPOptimizer : public MachineFunctionPass {
 public:
   static char ID;
-
   HexagonQFPOptimizer() : MachineFunctionPass(ID) {}
-
   bool runOnMachineFunction(MachineFunction &MF) override;
-
   bool optimizeQfp(MachineInstr *MI, MachineBasicBlock *MBB);
-
+  bool optimizeQfpTwoOp(MachineInstr *MI, MachineBasicBlock *MBB);
+  bool optimizeQfpOneOp(MachineInstr *MI, MachineBasicBlock *MBB);
   StringRef getPassName() const override { return HEXAGON_QFP_OPTIMIZER; }
-
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesCFG();
     MachineFunctionPass::getAnalysisUsage(AU);
   }
-
 private:
   const HexagonSubtarget *HST = nullptr;
   const HexagonInstrInfo *HII = nullptr;
   const MachineRegisterInfo *MRI = nullptr;
 };
-
 char HexagonQFPOptimizer::ID = 0;
 } // namespace
-
 INITIALIZE_PASS(HexagonQFPOptimizer, "hexagon-qfp-optimizer",
                 HEXAGON_QFP_OPTIMIZER, false, false)
-
 FunctionPass *llvm::createHexagonQFPOptimizer() {
   return new HexagonQFPOptimizer();
 }
 
 bool HexagonQFPOptimizer::optimizeQfp(MachineInstr *MI,
                                       MachineBasicBlock *MBB) {
-
-  // Early exit:
-  // - if instruction is invalid or has too few operands (QFP ops need 2 sources
-  // + 1 dest),
-  // - or does not have a transformation mapping.
-  if (MI->getNumOperands() < 3)
+  if (MI->getNumOperands() == 2)
+    return optimizeQfpOneOp(MI, MBB);
+  else if (MI->getNumOperands() == 3)
+    return optimizeQfpTwoOp(MI, MBB);
+  else
     return false;
+}
+
+bool HexagonQFPOptimizer::optimizeQfpOneOp(MachineInstr *MI,
+                                           MachineBasicBlock *MBB) {
+  unsigned Op0F = 0;
   auto It = QFPInstMap.find(MI->getOpcode());
   if (It == QFPInstMap.end())
     return false;
   unsigned short InstTy = It->second;
+  // Get the reachind defs of MI
+  MachineInstr *DefMI = MRI->getVRegDef(MI->getOperand(1).getReg());
+  MachineOperand &Res = MI->getOperand(0);
+  if (!Res.isReg())
+    return false;
+  LLVM_DEBUG(dbgs() << "\n[Reaching Defs of operands]: "; DefMI->dump());
+  MachineInstr *ReachDefDef = nullptr;
+  // Get the reaching def of the reaching def to check for W reg def
+  if (DefMI->getNumOperands() > 1 && DefMI->getOperand(1).isReg() &&
+      DefMI->getOperand(1).getReg().isVirtual())
+    ReachDefDef = MRI->getVRegDef(DefMI->getOperand(1).getReg());
+  unsigned ReachDefOp = DefMI->getOpcode();
+  MachineInstrBuilder MIB;
+  // Check if the reaching def is a conversion
+  if (ReachDefOp == Hexagon::V6_vconv_sf_qf32 ||
+      ReachDefOp == Hexagon::V6_vconv_hf_qf16) {
+    // Return if the reaching def of reaching def is W type
+    if (ReachDefDef && MRI->getRegClass(ReachDefDef->getOperand(0).getReg()) ==
+                           &Hexagon::HvxWRRegClass)
+      return false;
+    // Analyze the use operands of the conversion to get their KILL status
+    MachineOperand &SrcOp = DefMI->getOperand(1);
+    Op0F = getKillRegState(SrcOp.isKill());
+    SrcOp.setIsKill(false);
+    MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), HII->get(InstTy), Res.getReg())
+              .addReg(SrcOp.getReg(), Op0F, SrcOp.getSubReg());
+    LLVM_DEBUG(dbgs() << "\n[Inserting]: "; MIB.getInstr()->dump());
+    return true;
+  }
+  return false;
+}
 
+bool HexagonQFPOptimizer::optimizeQfpTwoOp(MachineInstr *MI,
+                                           MachineBasicBlock *MBB) {
   unsigned Op0F = 0;
   unsigned Op1F = 0;
+  auto It = QFPInstMap.find(MI->getOpcode());
+  if (It == QFPInstMap.end())
+    return false;
+  unsigned short InstTy = It->second;
   // Get the reaching defs of MI, DefMI1 and DefMI2
   MachineInstr *DefMI1 = nullptr;
   MachineInstr *DefMI2 = nullptr;
-
   if (MI->getOperand(1).isReg())
     DefMI1 = MRI->getVRegDef(MI->getOperand(1).getReg());
   if (MI->getOperand(2).isReg())
     DefMI2 = MRI->getVRegDef(MI->getOperand(2).getReg());
   if (!DefMI1 || !DefMI2)
     return false;
-
   MachineOperand &Res = MI->getOperand(0);
+  if (!Res.isReg())
+    return false;
   MachineInstr *Inst1 = nullptr;
   MachineInstr *Inst2 = nullptr;
   LLVM_DEBUG(dbgs() << "\n[Reaching Defs of operands]: "; DefMI1->dump();
              DefMI2->dump());
-
   // Get the reaching defs of DefMI
   if (DefMI1->getNumOperands() > 1 && DefMI1->getOperand(1).isReg() &&
       DefMI1->getOperand(1).getReg().isVirtual())
     Inst1 = MRI->getVRegDef(DefMI1->getOperand(1).getReg());
-
   if (DefMI2->getNumOperands() > 1 && DefMI2->getOperand(1).isReg() &&
       DefMI2->getOperand(1).getReg().isVirtual())
     Inst2 = MRI->getVRegDef(DefMI2->getOperand(1).getReg());
-
   unsigned Def1OP = DefMI1->getOpcode();
   unsigned Def2OP = DefMI2->getOpcode();
-
   MachineInstrBuilder MIB;
-  // Case 1: Both reaching defs of MI are qf to sf/hf conversions
+  // Check if the both the reaching defs of MI are qf to sf/hf conversions
   if ((Def1OP == Hexagon::V6_vconv_sf_qf32 &&
        Def2OP == Hexagon::V6_vconv_sf_qf32) ||
       (Def1OP == Hexagon::V6_vconv_hf_qf16 &&
        Def2OP == Hexagon::V6_vconv_hf_qf16)) {
-
     // If the reaching defs of DefMI are W register type, we return
     if ((Inst1 && Inst1->getNumOperands() > 0 && Inst1->getOperand(0).isReg() &&
          MRI->getRegClass(Inst1->getOperand(0).getReg()) ==
@@ -199,17 +242,13 @@ bool HexagonQFPOptimizer::optimizeQfp(MachineInstr *MI,
          MRI->getRegClass(Inst2->getOperand(0).getReg()) ==
              &Hexagon::HvxWRRegClass))
       return false;
-
     // Analyze the use operands of the conversion to get their KILL status
     MachineOperand &Src1 = DefMI1->getOperand(1);
     MachineOperand &Src2 = DefMI2->getOperand(1);
-
     Op0F = getKillRegState(Src1.isKill());
     Src1.setIsKill(false);
-
     Op1F = getKillRegState(Src2.isKill());
     Src2.setIsKill(false);
-
     if (MI->getOpcode() != Hexagon::V6_vmpy_qf32_sf) {
       auto OuterIt = QFPInstMap.find(MI->getOpcode());
       if (OuterIt == QFPInstMap.end())
@@ -219,28 +258,23 @@ bool HexagonQFPOptimizer::optimizeQfp(MachineInstr *MI,
         return false;
       InstTy = InnerIt->second;
     }
-
     MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), HII->get(InstTy), Res.getReg())
               .addReg(Src1.getReg(), Op0F, Src1.getSubReg())
               .addReg(Src2.getReg(), Op1F, Src2.getSubReg());
     LLVM_DEBUG(dbgs() << "\n[Inserting]: "; MIB.getInstr()->dump());
     return true;
-
-    // Case 2: Left operand is conversion to sf/hf
+    // Check if left operand's reaching def is a conversion to sf/hf
   } else if (((Def1OP == Hexagon::V6_vconv_sf_qf32 &&
                Def2OP != Hexagon::V6_vconv_sf_qf32) ||
               (Def1OP == Hexagon::V6_vconv_hf_qf16 &&
                Def2OP != Hexagon::V6_vconv_hf_qf16)) &&
              !DefMI2->isPHI() &&
              (MI->getOpcode() != Hexagon::V6_vmpy_qf32_sf)) {
-
     if (Inst1 && MRI->getRegClass(Inst1->getOperand(0).getReg()) ==
                      &Hexagon::HvxWRRegClass)
       return false;
-
     MachineOperand &Src1 = DefMI1->getOperand(1);
     MachineOperand &Src2 = MI->getOperand(2);
-
     Op0F = getKillRegState(Src1.isKill());
     Src1.setIsKill(false);
     Op1F = getKillRegState(Src2.isKill());
@@ -249,57 +283,58 @@ bool HexagonQFPOptimizer::optimizeQfp(MachineInstr *MI,
               .addReg(Src2.getReg(), Op1F, Src2.getSubReg());
     LLVM_DEBUG(dbgs() << "\n[Inserting]: "; MIB.getInstr()->dump());
     return true;
-
-    // Case 2: Left operand is conversion to sf/hf
+    // Check if right operand's reaching def is a conversion to sf/hf
   } else if (((Def1OP != Hexagon::V6_vconv_sf_qf32 &&
                Def2OP == Hexagon::V6_vconv_sf_qf32) ||
               (Def1OP != Hexagon::V6_vconv_hf_qf16 &&
                Def2OP == Hexagon::V6_vconv_hf_qf16)) &&
              !DefMI1->isPHI() &&
              (MI->getOpcode() != Hexagon::V6_vmpy_qf32_sf)) {
     // The second operand of original instruction is converted.
-    // In "mix" instructions, "qf" operand is always the first operand.
-
-    // Caveat: vsub is not commutative w.r.t operands.
-    if (InstTy == Hexagon::V6_vsub_qf16_mix ||
-        InstTy == Hexagon::V6_vsub_qf32_mix)
-      return false;
-
     if (Inst2 && MRI->getRegClass(Inst2->getOperand(0).getReg()) ==
                      &Hexagon::HvxWRRegClass)
       return false;
-
     MachineOperand &Src1 = MI->getOperand(1);
     MachineOperand &Src2 = DefMI2->getOperand(1);
-
     Op1F = getKillRegState(Src2.isKill());
     Src2.setIsKill(false);
     Op0F = getKillRegState(Src1.isKill());
-    MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), HII->get(InstTy), Res.getReg())
-              .addReg(Src2.getReg(), Op1F,
-                      Src2.getSubReg()) // Notice the operands are flipped.
-              .addReg(Src1.getReg(), Op0F, Src1.getSubReg());
+    if (InstTy == Hexagon::V6_vsub_qf16_mix ||
+        InstTy == Hexagon::V6_vsub_qf32_mix) {
+      if (!HST->useHVXV81Ops())
+        // vsub_(hf|sf)_mix insts are only avlbl on hvx81+
+        return false;
+      // vsub is not commutative w.r.t. operands -> treat it as a special case
+      // to choose the correct mix instruction.
+      if (Def2OP == Hexagon::V6_vconv_sf_qf32)
+        InstTy = Hexagon::V6_vsub_sf_mix;
+      else if (Def2OP == Hexagon::V6_vconv_hf_qf16)
+        InstTy = Hexagon::V6_vsub_hf_mix;
+      MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), HII->get(InstTy), Res.getReg())
+                .addReg(Src1.getReg(), Op0F, Src1.getSubReg())
+                .addReg(Src2.getReg(), Op1F, Src2.getSubReg());
+    } else {
+      MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), HII->get(InstTy), Res.getReg())
+                .addReg(Src2.getReg(), Op1F,
+                        Src2.getSubReg()) // Notice the operands are flipped.
+                .addReg(Src1.getReg(), Op0F, Src1.getSubReg());
+    }
     LLVM_DEBUG(dbgs() << "\n[Inserting]: "; MIB.getInstr()->dump());
     return true;
   }
-
   return false;
 }
 
 bool HexagonQFPOptimizer::runOnMachineFunction(MachineFunction &MF) {
-
   bool Changed = false;
-
   if (DisableQFOptimizer)
     return Changed;
-
   HST = &MF.getSubtarget<HexagonSubtarget>();
   if (!HST->useHVXV68Ops() || !HST->usePackets() ||
       skipFunction(MF.getFunction()))
     return false;
   HII = HST->getInstrInfo();
   MRI = &MF.getRegInfo();
-
   MachineFunction::iterator MBBI = MF.begin();
   LLVM_DEBUG(dbgs() << "\n=== Running QFPOptimzer Pass for : " << MF.getName()
                     << " Optimize intermediate conversions ===\n");
@@ -309,15 +344,18 @@ bool HexagonQFPOptimizer::runOnMachineFunction(MachineFunction &MF) {
     while (MII != MBBI->instr_end()) {
       MachineInstr *MI = &*MII;
       ++MII; // As MI might be removed.
-
-      if (QFPInstMap.count(MI->getOpcode()) &&
-          MI->getOpcode() != Hexagon::V6_vconv_sf_qf32 &&
-          MI->getOpcode() != Hexagon::V6_vconv_hf_qf16) {
-        LLVM_DEBUG(dbgs() << "\n###Analyzing for removal: "; MI->dump());
-        if (optimizeQfp(MI, MBB)) {
-          MI->eraseFromParent();
-          LLVM_DEBUG(dbgs() << "\t....Removing....");
-          Changed = true;
+      if (QFPInstMap.count(MI->getOpcode())) {
+        auto OpC = MI->getOpcode();
+        if (DisableQFOptForMul && HII->isQFPMul(MI))
+          continue;
+        if (OpC != Hexagon::V6_vconv_sf_qf32 &&
+            OpC != Hexagon::V6_vconv_hf_qf16) {
+          LLVM_DEBUG(dbgs() << "\n###Analyzing for removal: ";MI->dump());
+          if (optimizeQfp(MI, MBB)) {
+            MI->eraseFromParent();
+            LLVM_DEBUG(dbgs() << "\t....Removing....");
+            Changed = true;
+          }
         }
       }
     }