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[MachineOutliner] Preserve regmasks in calls to outlined functions
When emitting calls to an outlined function, the register masks from the outlined sequence are lost. The AArch64CollectLOH pass, which I plan to move to PreEmitPass2 (positioned after MachineOutliner), relies on accurate register masks. This patch ensures that regmasks are correctly preserved in the outlined calls, maintaining the required accuracy for subsequent passes.
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‎llvm/lib/CodeGen/MachineOutliner.cpp‎

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@@ -1117,6 +1117,7 @@ bool MachineOutliner::outline(
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// instruction. It also updates call site information for moved
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// code.
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SmallSet<Register, 2> UseRegs, DefRegs;
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SmallPtrSet<const uint32_t *, 2> RegMasks;
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// Copy over the defs in the outlined range.
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// First inst in outlined range <-- Anything that's defined in this
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// ... .. range has to be added as an
@@ -1130,6 +1131,12 @@ bool MachineOutliner::outline(
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MachineInstr *MI = &*Iter;
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SmallSet<Register, 2> InstrUseRegs;
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for (MachineOperand &MOP : MI->operands()) {
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// Collect all regmasks. Merge them in the end.
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if (MOP.isRegMask()) {
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RegMasks.insert(MOP.getRegMask());
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continue;
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}
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// Skip over anything that isn't a register.
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if (!MOP.isReg())
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continue;
@@ -1153,6 +1160,24 @@ bool MachineOutliner::outline(
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MI->getMF()->eraseCallSiteInfo(MI);
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}
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if (!RegMasks.empty()) {
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if (RegMasks.size() == 1) {
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CallInst->addOperand(
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MachineOperand::CreateRegMask(*RegMasks.begin()));
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} else {
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uint32_t *RegMask = MF->allocateRegMask();
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unsigned NumRegs =
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MF->getSubtarget().getRegisterInfo()->getNumRegs();
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unsigned Size = MachineOperand::getRegMaskSize(NumRegs);
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memset(RegMask, UINT32_MAX, Size * sizeof(RegMask[0]));
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for (const uint32_t *Mask : RegMasks) {
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for (unsigned I = 0; I < Size; ++I)
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RegMask[I] &= Mask[I];
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}
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CallInst->addOperand(MachineOperand::CreateRegMask(RegMask));
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}
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}
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for (const Register &I : DefRegs)
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// If it's a def, add it to the call instruction.
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CallInst->addOperand(

‎llvm/test/CodeGen/AArch64/machine-outliner-regmask.mir‎

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@@ -0,0 +1,94 @@
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# RUN: llc -mtriple=aarch64-apple-ios -run-pass=prologepilog -run-pass=machine-outliner %s -o - | FileCheck %s
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--- |
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declare swiftcc void @bar()
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declare void @baz(i32, i32, i32) #0
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define void @test_same_regmask() #0 {
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ret void
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}
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define void @test_different_regmasks() #0 {
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ret void
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}
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define void @foo(i32, i32, i32, i32, i32, i32, i32, i32) #0 {
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ret void
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}
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...
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---
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name: foo
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tracksRegLiveness: true
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body: |
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bb.0:
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RET undef $lr
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...
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---
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name: test_same_regmask
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: test_same_regmask
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; CHECK: bb.1:
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; CHECK-NEXT: BL @OUTLINED_FUNCTION_1, csr_aarch64_aapcs
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bb.0:
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$sp = frame-setup SUBXri $sp, 16, 0
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bb.1:
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$w0 = MOVZWi 1, 0
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$w1 = MOVZWi 2, 0
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$w2 = MOVZWi 3, 0
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BL @baz, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $w0, implicit killed $w1, implicit killed $w2, implicit-def $sp
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$w0 = MOVZWi 1, 0
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$w1 = MOVZWi 2, 0
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$w2 = MOVZWi 3, 0
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BL @baz, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $w0, implicit killed $w1, implicit killed $w2, implicit-def $sp
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$sp = ADDXri $sp, 16, 0
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RET undef $lr
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...
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---
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name: test_different_regmasks
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: test_different_regmasks
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; CHECK: bb.1:
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; CHECK-NEXT: BL @OUTLINED_FUNCTION_0, CustomRegMask($fp,$lr,$wzr,$wzr_hi,$xzr,$b8,$b9,$b10,$b11,$b12,$b13,$b14,$b15,$d8,$d9,$d10,$d11,$d12,$d13,$d14,$d15,$h8,$h9,$h10,$h11,$h12,$h13,$h14,$h15,$s8,$s9,$s10,$s11,$s12,$s13,$s14,$s15,$w19,$w20,$w22,$w23,$w24,$w25,$w26,$w27,$w28,$w29,$w30,$x19,$x20,$x22,$x23,$x24,$x25,$x26,$x27,$x28,$b8_hi,$b9_hi,$b10_hi,$b11_hi,$b12_hi,$b13_hi,$b14_hi,$b15_hi,$h8_hi,$h9_hi,$h10_hi,$h11_hi,$h12_hi,$h13_hi,$h14_hi,$h15_hi,$s8_hi,$s9_hi,$s10_hi,$s11_hi,$s12_hi,$s13_hi,$s14_hi,$s15_hi,$w19_hi,$w20_hi,$w22_hi,$w23_hi,$w24_hi,$w25_hi,$w26_hi,$w27_hi,$w28_hi,$w29_hi,$w30_hi,$d8_d9,$d9_d10,$d10_d11,$d11_d12,$d12_d13,$d13_d14,$d14_d15,$d8_d9_d10_d11,$d9_d10_d11_d12,$d10_d11_d12_d13,$d11_d12_d13_d14,$d12_d13_d14_d15,$d8_d9_d10,$d9_d10_d11,$d10_d11_d12,$d11_d12_d13,$d12_d13_d14,$d13_d14_d15,$x22_x23_x24_x25_x26_x27_x28_fp,$w22_w23,$w24_w25,$w26_w27,$w28_w29,$x28_fp,$x22_x23,$x24_x25,$x26_x27)
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bb.0:
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$sp = frame-setup SUBXri $sp, 16, 0
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bb.1:
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$w0 = MOVZWi 1, 0
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$w1 = MOVZWi 2, 0
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$w2 = MOVZWi 3, 0
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$w3 = MOVZWi 4, 0
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$w4 = MOVZWi 5, 0
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$w5 = MOVZWi 6, 0
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$w6 = MOVZWi 7, 0
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$w7 = MOVZWi 8, 0
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BL @foo, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $w0, implicit killed $w1, implicit killed $w2, implicit killed $w3, implicit killed $w4, implicit killed $w5, implicit killed $w6, implicit killed $w7, implicit-def $sp
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BL @bar, csr_aarch64_aapcs_swifterror, implicit-def dead $lr, implicit $sp, implicit-def $sp
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$w0 = MOVZWi 1, 0
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$w1 = MOVZWi 2, 0
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$w2 = MOVZWi 3, 0
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$w3 = MOVZWi 4, 0
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$w4 = MOVZWi 5, 0
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$w5 = MOVZWi 6, 0
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$w6 = MOVZWi 7, 0
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$w7 = MOVZWi 8, 0
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BL @foo, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $w0, implicit killed $w1, implicit killed $w2, implicit killed $w3, implicit killed $w4, implicit killed $w5, implicit killed $w6, implicit killed $w7, implicit-def $sp
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BL @bar, csr_aarch64_aapcs_swifterror, implicit-def dead $lr, implicit $sp, implicit-def $sp
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$w0 = MOVZWi 1, 0
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$w1 = MOVZWi 2, 0
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$w2 = MOVZWi 3, 0
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$w3 = MOVZWi 4, 0
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$w4 = MOVZWi 5, 0
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$w5 = MOVZWi 6, 0
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$w6 = MOVZWi 7, 0
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$w7 = MOVZWi 8, 0
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BL @foo, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $w0, implicit killed $w1, implicit killed $w2, implicit killed $w3, implicit killed $w4, implicit killed $w5, implicit killed $w6, implicit killed $w7, implicit-def $sp
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BL @bar, csr_aarch64_aapcs_swifterror, implicit-def dead $lr, implicit $sp, implicit-def $sp
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$sp = ADDXri $sp, 16, 0
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RET undef $lr

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