Address comments

Author: V-FEXrt

llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

@@ -258,17 +258,11 @@ class SPIRVInstructionSelector : public InstructionSelector {
                          MachineInstr &I) const;
 
   bool selectWaveNOpInst(Register ResVReg, const SPIRVType *ResType,
-                         MachineInstr &I, unsigned Opcode,
-                         unsigned OperandCount) const;
-  bool selectWaveActiveAnyTrue(Register ResVReg, const SPIRVType *ResType,
-                               MachineInstr &I) const;
+                         MachineInstr &I, unsigned Opcode) const;
 
   bool selectWaveActiveCountBits(Register ResVReg, const SPIRVType *ResType,
                                  MachineInstr &I) const;
 
-  bool selectWaveReadLaneAt(Register ResVReg, const SPIRVType *ResType,
-                            MachineInstr &I) const;
-
   bool selectUnmergeValues(MachineInstr &I) const;
 
   bool selectHandleFromBinding(Register &ResVReg, const SPIRVType *ResType,
@@ -1958,13 +1952,7 @@ bool SPIRVInstructionSelector::selectSign(Register ResVReg,
 bool SPIRVInstructionSelector::selectWaveNOpInst(Register ResVReg,
                                                  const SPIRVType *ResType,
                                                  MachineInstr &I,
-                                                 unsigned Opcode,
-                                                 unsigned OperandCount) const {
-  assert(I.getNumOperands() == OperandCount);
-  for (unsigned j = 2; j < OperandCount; j++) {
-    assert(I.getOperand(j).isReg());
-  }
-
+                                                 unsigned Opcode) const {
   MachineBasicBlock &BB = *I.getParent();
   SPIRVType *IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII);
 
@@ -1974,27 +1962,21 @@ bool SPIRVInstructionSelector::selectWaveNOpInst(Register ResVReg,
                  .addUse(GR.getOrCreateConstInt(SPIRV::Scope::Subgroup, I,
                                                 IntTy, TII));
 
-  for (unsigned j = 2; j < OperandCount; j++) {
+  for (unsigned j = 2; j < I.getNumOperands(); j++) {
     BMI.addUse(I.getOperand(j).getReg());
   }
 
   return BMI.constrainAllUses(TII, TRI, RBI);
 }
 
-bool SPIRVInstructionSelector::selectWaveActiveAnyTrue(Register ResVReg,
-                                                       const SPIRVType *ResType,
-                                                       MachineInstr &I) const {
-  return selectWaveNOpInst(ResVReg, ResType, I, SPIRV::OpGroupNonUniformAny, 3);
-}
-
 bool SPIRVInstructionSelector::selectWaveActiveCountBits(
     Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const {
 
   SPIRVType *IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII);
   SPIRVType *BallotType = GR.getOrCreateSPIRVVectorType(IntTy, 4, I, TII);
   Register BallotReg = MRI->createVirtualRegister(GR.getRegClass(BallotType));
   bool Result = selectWaveNOpInst(BallotReg, BallotType, I,
-                                  SPIRV::OpGroupNonUniformBallot, 3);
+                                  SPIRV::OpGroupNonUniformBallot);
 
   MachineBasicBlock &BB = *I.getParent();
   Result &=
@@ -2010,13 +1992,6 @@ bool SPIRVInstructionSelector::selectWaveActiveCountBits(
   return Result;
 }
 
-bool SPIRVInstructionSelector::selectWaveReadLaneAt(Register ResVReg,
-                                                    const SPIRVType *ResType,
-                                                    MachineInstr &I) const {
-  return selectWaveNOpInst(ResVReg, ResType, I, SPIRV::OpGroupNonUniformShuffle,
-                           4);
-}
-
 bool SPIRVInstructionSelector::selectBitreverse(Register ResVReg,
                                                 const SPIRVType *ResType,
                                                 MachineInstr &I) const {
@@ -2844,7 +2819,7 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
   case Intrinsic::spv_wave_active_countbits:
     return selectWaveActiveCountBits(ResVReg, ResType, I);
   case Intrinsic::spv_wave_any:
-    return selectWaveActiveAnyTrue(ResVReg, ResType, I);
+    return selectWaveNOpInst(ResVReg, ResType, I, SPIRV::OpGroupNonUniformAny);
   case Intrinsic::spv_wave_is_first_lane: {
     SPIRVType *IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII);
     return BuildMI(BB, I, I.getDebugLoc(),
@@ -2854,7 +2829,8 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
         .addUse(GR.getOrCreateConstInt(3, I, IntTy, TII));
   }
   case Intrinsic::spv_wave_readlane:
-    return selectWaveReadLaneAt(ResVReg, ResType, I);
+    return selectWaveNOpInst(ResVReg, ResType, I,
+                             SPIRV::OpGroupNonUniformShuffle);
   case Intrinsic::spv_step:
     return selectExtInst(ResVReg, ResType, I, CL::step, GL::Step);
   case Intrinsic::spv_radians: