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9 files changed

+53
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lines changed

‎llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp‎

Lines changed: 11 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1259,13 +1259,17 @@ void PPCAsmParser::processInstruction(MCInst &Inst,
12591259
static std::string PPCMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS,
12601260
unsigned VariantID = 0);
12611261

1262-
static bool hasMemOp(const OperandVector &Operands) {
1263-
for (const auto &Operand : Operands) {
1264-
const PPCOperand &Op = static_cast<const PPCOperand &>(*Operand);
1265-
if (Op.isMemOpBase())
1266-
return true;
1262+
// Check that the register+immediate memory operand is in the right position and
1263+
// is expected by the instruction
1264+
static bool validateMemOp(const OperandVector &Operands, bool isMemriOp) {
1265+
for (size_t idx = 0; idx < Operands.size(); ++idx) {
1266+
const PPCOperand &Op = static_cast<const PPCOperand &>(*Operands[idx]);
1267+
if ((idx == 3 && Op.isMemOpBase() != isMemriOp) ||
1268+
(idx != 3 && Op.isMemOpBase())) {
1269+
return false;
1270+
}
12671271
}
1268-
return false;
1272+
return true;
12691273
}
12701274

12711275
bool PPCAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
@@ -1277,7 +1281,7 @@ bool PPCAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
12771281

12781282
switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
12791283
case Match_Success:
1280-
if (hasMemOp(Operands) != TII->isMemOp(Inst.getOpcode()))
1284+
if (!validateMemOp(Operands, TII->isMemriOp(Inst.getOpcode())))
12811285
return Error(IDLoc, "invalid operand for instruction");
12821286
// Post-process instructions (typically extended mnemonics)
12831287
processInstruction(Inst, Operands);

‎llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -172,8 +172,8 @@ enum {
172172
SExt32To64 = 0x1 << (NewDef_Shift + 2),
173173
/// This instruction produced a zero extended result.
174174
ZExt32To64 = 0x1 << (NewDef_Shift + 3),
175-
/// This instruction uses a memory operand.
176-
MemOp = 0x1 << (NewDef_Shift + 4)
175+
/// This instruction takes a register+immediate memory operand.
176+
MemriOp = 0x1 << (NewDef_Shift + 4)
177177
};
178178
} // end namespace PPCII
179179

‎llvm/lib/Target/PowerPC/PPCInstr64Bit.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -777,7 +777,7 @@ def ADDIS8 : DForm_2<15, (outs g8rc:$RST), (ins g8rc_nox0:$RA, s17imm64:$D),
777777
def LA8 : DForm_2<14, (outs g8rc:$RST), (ins g8rc_nox0:$RA, s16imm64:$D),
778778
"la $RST, $D($RA)", IIC_IntGeneral,
779779
[(set i64:$RST, (add i64:$RA,
780-
(PPClo tglobaladdr:$D, 0)))]>, MemOp;
780+
(PPClo tglobaladdr:$D, 0)))]>, MemriOp;
781781

782782
let Defs = [CARRY] in {
783783
def SUBFIC8: DForm_2< 8, (outs g8rc:$RST), (ins g8rc:$RA, s16imm64:$D),

‎llvm/lib/Target/PowerPC/PPCInstrFormats.td‎

Lines changed: 12 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -55,9 +55,9 @@ class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
5555
bits<1> ZExt32To64 = 0;
5656
let TSFlags{9} = ZExt32To64;
5757

58-
// Indicate that this instruction uses a memory operand.
59-
bits<1> MemOp = 0;
60-
let TSFlags{10} = MemOp;
58+
// Indicate that this instruction takes a register+immediate memory operand.
59+
bits<1> MemriOp = 0;
60+
let TSFlags{10} = MemriOp;
6161

6262
// Fields used for relation models.
6363
string BaseName = "";
@@ -86,7 +86,7 @@ class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
8686
class XFormMemOp { bits<1> XFormMemOp = 1; }
8787
class SExt32To64 { bits<1> SExt32To64 = 1; }
8888
class ZExt32To64 { bits<1> ZExt32To64 = 1; }
89-
class MemOp { bits<1> MemOp = 1; }
89+
class MemriOp { bits<1> MemriOp = 1; }
9090

9191
// Two joined instructions; used to emit two adjacent instructions as one.
9292
// The itinerary from the first instruction is used for scheduling and
@@ -120,10 +120,6 @@ class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
120120
let TSFlags{2} = PPC970_Cracked;
121121
let TSFlags{5-3} = PPC970_Unit;
122122

123-
// Indicate that this instruction uses a memory operand.
124-
bits<1> MemOp = 0;
125-
let TSFlags{10} = MemOp;
126-
127123
// Fields used for relation models.
128124
string BaseName = "";
129125
bit Interpretation64Bit = 0;
@@ -259,7 +255,7 @@ class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
259255

260256
class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
261257
InstrItinClass itin, list<dag> pattern>
262-
: DForm_base<opcode, OOL, IOL, asmstr, itin, pattern>, MemOp {
258+
: DForm_base<opcode, OOL, IOL, asmstr, itin, pattern>, MemriOp {
263259
}
264260

265261
class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
@@ -304,7 +300,7 @@ class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
304300
let RST = 0;
305301
let RA = 0;
306302
let D = 0;
307-
let MemOp = 0;
303+
let MemriOp = 0;
308304
}
309305

310306
class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL,
@@ -382,7 +378,7 @@ class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
382378
// 1.7.5 DS-Form
383379
class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
384380
InstrItinClass itin, list<dag> pattern>
385-
: I<opcode, OOL, IOL, asmstr, itin>, MemOp {
381+
: I<opcode, OOL, IOL, asmstr, itin>, MemriOp {
386382
bits<5> RST;
387383
bits<5> RA;
388384
bits<14> D;
@@ -414,7 +410,7 @@ class DXForm<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
414410
// DQ-Form: [PO T RA DQ TX XO] or [PO S RA DQ SX XO]
415411
class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
416412
string asmstr, InstrItinClass itin, list<dag> pattern>
417-
: I<opcode, OOL, IOL, asmstr, itin>, MemOp {
413+
: I<opcode, OOL, IOL, asmstr, itin>, MemriOp {
418414
bits<6> XT;
419415
bits<5> RA;
420416
bits<12> DQ;
@@ -431,7 +427,7 @@ class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
431427
class DQForm_RTp5_RA17_MEM<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
432428
string asmstr, InstrItinClass itin,
433429
list<dag> pattern>
434-
: I<opcode, OOL, IOL, asmstr, itin>, MemOp {
430+
: I<opcode, OOL, IOL, asmstr, itin>, MemriOp {
435431
bits<5> RTp;
436432
bits<5> RA;
437433
bits<12> DQ;
@@ -1256,7 +1252,7 @@ class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2,
12561252

12571253
class XForm_XD6_RA5_RB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
12581254
string asmstr, InstrItinClass itin, list<dag> pattern>
1259-
: I<opcode, OOL, IOL, asmstr, itin>, MemOp {
1255+
: I<opcode, OOL, IOL, asmstr, itin>, MemriOp {
12601256
bits<5> RA;
12611257
bits<6> D;
12621258
bits<5> RB;
@@ -1665,7 +1661,7 @@ class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1,
16651661
dag OOL, dag IOL, string asmstr,
16661662
InstrItinClass itin, list<dag> pattern>
16671663
: XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2,
1668-
OOL, IOL, asmstr, itin, pattern>, MemOp {
1664+
OOL, IOL, asmstr, itin, pattern> {
16691665
let BO = bo;
16701666
let BI = bi;
16711667
let BH = 0;
@@ -1675,7 +1671,7 @@ class XLForm_2_ext_and_DForm_1<bits<6> opcode1, bits<10> xo1, bits<5> bo,
16751671
bits<5> bi, bit lk, bits<6> opcode2, dag OOL,
16761672
dag IOL, string asmstr, InstrItinClass itin,
16771673
list<dag> pattern>
1678-
: I2<opcode1, opcode2, OOL, IOL, asmstr, itin>, MemOp {
1674+
: I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
16791675

16801676
bits<5> RST;
16811677
bits<5> RA;

‎llvm/lib/Target/PowerPC/PPCInstrInfo.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -285,8 +285,8 @@ class PPCInstrInfo : public PPCGenInstrInfo {
285285
bool isZExt32To64(unsigned Opcode) const {
286286
return get(Opcode).TSFlags & PPCII::ZExt32To64;
287287
}
288-
bool isMemOp(unsigned Opcode) const {
289-
return get(Opcode).TSFlags & PPCII::MemOp;
288+
bool isMemriOp(unsigned Opcode) const {
289+
return get(Opcode).TSFlags & PPCII::MemriOp;
290290
}
291291

292292
static bool isSameClassPhysRegCopy(unsigned Opcode) {

‎llvm/lib/Target/PowerPC/PPCInstrInfo.td‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2303,7 +2303,7 @@ let isCodeGenOnly = 1 in
23032303
def LA : DForm_2<14, (outs gprc:$RST), (ins gprc_nor0:$RA, s16imm:$D),
23042304
"la $RST, $D($RA)", IIC_IntGeneral,
23052305
[(set i32:$RST, (add i32:$RA,
2306-
(PPClo tglobaladdr:$D, 0)))]>, MemOp;
2306+
(PPClo tglobaladdr:$D, 0)))]>, MemriOp;
23072307
def MULLI : DForm_2< 7, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D),
23082308
"mulli $RST, $RA, $D", IIC_IntMulLI,
23092309
[(set i32:$RST, (mul i32:$RA, imm32SExt16:$D))]>;
@@ -3467,9 +3467,9 @@ class PPCAsmPseudo<string asm, dag iops>
34673467
let isPseudo = 1;
34683468
let hasNoSchedulingInfo = 1;
34693469

3470-
// Indicate that this instruction uses a memory operand.
3471-
bits<1> MemOp = 0;
3472-
let TSFlags{10} = MemOp;
3470+
// Indicate that this instruction takes a register+immediate memory operand.
3471+
bits<1> MemriOp = 0;
3472+
let TSFlags{10} = MemriOp;
34733473
}
34743474

34753475
// Prefixed instructions may require access to the above defs at a later
@@ -4718,7 +4718,7 @@ def : InstAlias<"tlbilxva $RA, $RB", (TLBILX 3, gprc:$RA, gprc:$RB)>,
47184718
Requires<[IsBookE]>;
47194719
def : InstAlias<"tlbilxva $RB", (TLBILX 3, R0, gprc:$RB)>, Requires<[IsBookE]>;
47204720

4721-
def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>, MemOp;
4721+
def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>, MemriOp;
47224722

47234723
def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
47244724
(ins gprc:$rA, gprc:$rB, s16imm:$imm)>;

‎llvm/lib/Target/PowerPC/PPCInstrP10.td‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -138,9 +138,9 @@ class PI<bits<6> pref, bits<6> opcode, dag OOL, dag IOL, string asmstr,
138138
bits<1> Prefixed = 1; // This is a prefixed instruction.
139139
let TSFlags{7} = Prefixed;
140140

141-
// Indicate that this instruction uses a memory operand.
142-
bits<1> MemOp = 0;
143-
let TSFlags{10} = MemOp;
141+
// Indicate that this instruction takes a register+immediate memory operand.
142+
bits<1> MemriOp = 0;
143+
let TSFlags{10} = MemriOp;
144144

145145
// For cases where multiple instruction definitions really represent the
146146
// same underlying instruction but with one definition for 64-bit arguments
@@ -187,7 +187,7 @@ multiclass VXForm_VTB5_RCr<bits<10> xo, bits<5> R, dag OOL, dag IOL,
187187

188188
class MLS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
189189
InstrItinClass itin, list<dag> pattern>
190-
: PI<1, opcode, OOL, IOL, asmstr, itin>, MemOp {
190+
: PI<1, opcode, OOL, IOL, asmstr, itin>, MemriOp {
191191
bits<5> RST;
192192
bits<5> RA;
193193
bits<34> D;
@@ -261,7 +261,7 @@ multiclass MLS_DForm_R_SI34_RTA5_p<bits<6> opcode, dag OOL, dag IOL,
261261

262262
class 8LS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
263263
InstrItinClass itin, list<dag> pattern>
264-
: PI<1, opcode, OOL, IOL, asmstr, itin>, MemOp {
264+
: PI<1, opcode, OOL, IOL, asmstr, itin>, MemriOp {
265265
bits<5> RST;
266266
bits<5> RA;
267267
bits<34> D;
@@ -285,7 +285,7 @@ class 8LS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
285285
class 8LS_DForm_R_SI34_XT6_RA5_MEM<bits<5> opcode, dag OOL, dag IOL,
286286
string asmstr, InstrItinClass itin,
287287
list<dag> pattern>
288-
: PI<1, { opcode, ? }, OOL, IOL, asmstr, itin>, MemOp {
288+
: PI<1, { opcode, ? }, OOL, IOL, asmstr, itin>, MemriOp {
289289
bits<6> XST;
290290
bits<5> RA;
291291
bits<34> D;
@@ -589,7 +589,7 @@ multiclass MLS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL,
589589
isPCRel;
590590
let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in {
591591
def nopc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL, asmstr, itin, []>;
592-
let RA = 0, MemOp = 0 in
592+
let RA = 0, MemriOp = 0 in
593593
def onlypc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRelOnly_IOL,
594594
asmstr_pcext, itin, []>, isPCRel;
595595
}
@@ -606,7 +606,7 @@ multiclass 8LS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL,
606606
isPCRel;
607607
let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in {
608608
def nopc : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL, asmstr, itin, []>;
609-
let RA = 0, MemOp = 0 in
609+
let RA = 0, MemriOp = 0 in
610610
def onlypc : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRelOnly_IOL,
611611
asmstr_pcext, itin, []>, isPCRel;
612612
}
@@ -623,7 +623,7 @@ multiclass 8LS_DForm_R_SI34_XT6_RA5_MEM_p<bits<5> opcode, dag OOL, dag IOL,
623623
isPCRel;
624624
let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in {
625625
def nopc : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, IOL, asmstr, itin, []>;
626-
let RA = 0, MemOp = 0 in
626+
let RA = 0, MemriOp = 0 in
627627
def onlypc : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, PCRelOnly_IOL,
628628
asmstr_pcext, itin, []>, isPCRel;
629629
}
@@ -851,7 +851,7 @@ let Predicates = [PrefixInstrs, HasP10Vector] in {
851851

852852
class DQForm_XTp5_RA17_MEM<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
853853
string asmstr, InstrItinClass itin, list<dag> pattern>
854-
: I<opcode, OOL, IOL, asmstr, itin>, MemOp {
854+
: I<opcode, OOL, IOL, asmstr, itin>, MemriOp {
855855
bits<5> XTp;
856856
bits<5> RA;
857857
bits<12> DQ;
@@ -883,7 +883,7 @@ class XForm_XTp5_XAB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
883883

884884
class 8LS_DForm_R_XTp5_SI34_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
885885
InstrItinClass itin, list<dag> pattern>
886-
: PI<1, opcode, OOL, IOL, asmstr, itin>, MemOp {
886+
: PI<1, opcode, OOL, IOL, asmstr, itin>, MemriOp {
887887
bits<5> XTp;
888888
bits<5> RA;
889889
bits<34> D;
@@ -914,7 +914,7 @@ multiclass 8LS_DForm_R_XTp5_SI34_MEM_p<bits<6> opcode, dag OOL,
914914
isPCRel;
915915
let isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in {
916916
def nopc : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, IOL, asmstr, itin, []>;
917-
let RA = 0, MemOp = 0 in
917+
let RA = 0, MemriOp = 0 in
918918
def onlypc : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, PCRelOnly_IOL,
919919
asmstr_pcext, itin, []>, isPCRel;
920920
}
@@ -2510,7 +2510,7 @@ let Predicates = [IsISA3_1, PrefixInstrs], isAsmParserOnly = 1, hasNoSchedulingI
25102510
let Interpretation64Bit = 1 in {
25112511
def PLA8 : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT),
25122512
(ins g8rc_nox0:$RA, s34imm:$SI),
2513-
"pla $RT, ${SI} ${RA}", IIC_IntSimple, []>, MemOp;
2513+
"pla $RT, ${SI} ${RA}", IIC_IntSimple, []>, MemriOp;
25142514
def PLA8pc : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT),
25152515
(ins s34imm_pcrel:$SI),
25162516
"pla $RT, $SI", IIC_IntSimple, []>, isPCRel;
@@ -2521,7 +2521,7 @@ let Predicates = [IsISA3_1, PrefixInstrs], isAsmParserOnly = 1, hasNoSchedulingI
25212521

25222522
def PLA : MLS_DForm_SI34_RT5<14, (outs gprc:$RT),
25232523
(ins gprc_nor0:$RA, s34imm:$SI),
2524-
"pla $RT, ${SI} ${RA}", IIC_IntSimple, []>, MemOp;
2524+
"pla $RT, ${SI} ${RA}", IIC_IntSimple, []>, MemriOp;
25252525
def PLApc : MLS_DForm_SI34_RT5<14, (outs gprc:$RT),
25262526
(ins s34imm_pcrel:$SI),
25272527
"pla $RT, $SI", IIC_IntSimple, []>, isPCRel;

‎llvm/lib/Target/PowerPC/PPCInstrSPE.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -114,7 +114,7 @@ class EVXForm_4<bits<8> xo, dag OOL, dag IOL, string asmstr,
114114

115115
class EVXForm_D<bits<11> xo, dag OOL, dag IOL, string asmstr,
116116
InstrItinClass itin, list<dag> pattern> :
117-
I<4, OOL, IOL, asmstr, itin>, MemOp {
117+
I<4, OOL, IOL, asmstr, itin>, MemriOp {
118118
bits<5> RT;
119119
bits<5> RA;
120120
bits<5> D;

‎llvm/test/MC/PowerPC/ppc64-errors.s‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -153,3 +153,8 @@
153153
# CHECK: error: invalid operand for instruction
154154
# CHECK-NEXT: addi 3, 10(3)
155155
addi 3, 10(3)
156+
157+
# Invalid memory operand position
158+
# CHECK: error: invalid operand for instruction
159+
# CHECK-NEXT: la 0(3), 3
160+
la 0(3), 3

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