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Precommit tests for sinking vector ops
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‎llvm/test/CodeGen/AMDGPU/loop-vector-sink.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
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; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefix=OPT %s
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; testing insert case
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define amdgpu_kernel void @runningSum(ptr addrspace(1) %out0, ptr addrspace(1) %out1, i32 %inputElement0, i32 %inputElement1, i32 %inputIter) {
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; OPT-LABEL: define amdgpu_kernel void @runningSum(
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; OPT-SAME: ptr addrspace(1) [[OUT0:%.*]], ptr addrspace(1) [[OUT1:%.*]], i32 [[INPUTELEMENT0:%.*]], i32 [[INPUTELEMENT1:%.*]], i32 [[INPUTITER:%.*]]) #[[ATTR0:[0-9]+]] {
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; OPT-NEXT: [[PREHEADER:.*]]:
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; OPT-NEXT: [[VECELEMENT0:%.*]] = insertelement <2 x i32> poison, i32 [[INPUTELEMENT0]], i64 0
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; OPT-NEXT: [[BROADCAST0:%.*]] = shufflevector <2 x i32> [[VECELEMENT0]], <2 x i32> poison, <2 x i32> zeroinitializer
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; OPT-NEXT: [[VECELEMENT1:%.*]] = insertelement <2 x i32> poison, i32 [[INPUTELEMENT1]], i64 0
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; OPT-NEXT: [[TMP0:%.*]] = shufflevector <2 x i32> [[VECELEMENT1]], <2 x i32> poison, <2 x i32> zeroinitializer
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; OPT-NEXT: br label %[[LOOPBODY:.*]]
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; OPT: [[LOOPBODY]]:
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; OPT-NEXT: [[PREVIOUSSUM:%.*]] = phi <2 x i32> [ [[TMP0]], %[[PREHEADER]] ], [ [[RUNNINGSUM:%.*]], %[[LOOPBODY]] ]
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; OPT-NEXT: [[ITERCOUNT:%.*]] = phi i32 [ [[INPUTITER]], %[[PREHEADER]] ], [ [[ITERSLEFT:%.*]], %[[LOOPBODY]] ]
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; OPT-NEXT: [[RUNNINGSUM]] = add <2 x i32> [[TMP0]], [[PREVIOUSSUM]]
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; OPT-NEXT: [[ITERSLEFT]] = sub i32 [[ITERCOUNT]], 1
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; OPT-NEXT: [[COND:%.*]] = icmp eq i32 [[ITERSLEFT]], 0
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; OPT-NEXT: br i1 [[COND]], label %[[LOOPEXIT:.*]], label %[[LOOPBODY]]
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; OPT: [[LOOPEXIT]]:
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; OPT-NEXT: [[SUMELEMENT0:%.*]] = extractelement <2 x i32> [[RUNNINGSUM]], i64 0
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; OPT-NEXT: [[SUMELEMENT1:%.*]] = extractelement <2 x i32> [[RUNNINGSUM]], i64 1
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; OPT-NEXT: store i32 [[SUMELEMENT0]], ptr addrspace(1) [[OUT0]], align 4
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; OPT-NEXT: store i32 [[SUMELEMENT1]], ptr addrspace(1) [[OUT1]], align 4
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; OPT-NEXT: ret void
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;
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preheader:
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%vecElement0 = insertelement <2 x i32> poison, i32 %inputElement0, i64 0
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%broadcast0 = shufflevector <2 x i32> %vecElement0, <2 x i32> poison, <2 x i32> zeroinitializer
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%vecElement1 = insertelement <2 x i32> poison, i32 %inputElement1, i64 0
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%broadcast1 = shufflevector <2 x i32> %vecElement1, <2 x i32> poison, <2 x i32> zeroinitializer
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br label %loopBody
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loopBody:
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%previousSum = phi <2 x i32> [ %broadcast1, %preheader ], [ %runningSum, %loopBody ]
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%iterCount = phi i32 [ %inputIter, %preheader ], [ %itersLeft, %loopBody ]
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%runningSum = add <2 x i32> %broadcast1, %previousSum
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%itersLeft = sub i32 %iterCount, 1
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%cond = icmp eq i32 %itersLeft, 0
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br i1 %cond, label %loopExit, label %loopBody
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loopExit:
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%sumElement0 = extractelement <2 x i32> %runningSum, i64 0
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%sumElement1 = extractelement <2 x i32> %runningSum, i64 1
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store i32 %sumElement0, ptr addrspace(1) %out0
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store i32 %sumElement1, ptr addrspace(1) %out1
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ret void
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}
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; testing extract case with single use
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define amdgpu_kernel void @test_sink_extract_single_use_operands(ptr addrspace(1) %out0, <2 x i32> %inputVec) {
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; OPT-LABEL: define amdgpu_kernel void @test_sink_extract_single_use_operands(
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; OPT-SAME: ptr addrspace(1) [[OUT0:%.*]], <2 x i32> [[INPUTVEC:%.*]]) #[[ATTR0]] {
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; OPT-NEXT: [[ENTRY:.*:]]
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; OPT-NEXT: [[RUNNINGSUM:%.*]] = add <2 x i32> [[INPUTVEC]], splat (i32 1)
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; OPT-NEXT: [[SUMELEMENT0:%.*]] = extractelement <2 x i32> [[RUNNINGSUM]], i64 0
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; OPT-NEXT: [[RESULT:%.*]] = add i32 [[SUMELEMENT0]], 100
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; OPT-NEXT: store i32 [[RESULT]], ptr addrspace(1) [[OUT0]], align 4
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; OPT-NEXT: ret void
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;
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entry:
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%runningSum = add <2 x i32> %inputVec, <i32 1, i32 1>
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%sumElement0 = extractelement <2 x i32> %runningSum, i64 0
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%result = add i32 %sumElement0, 100
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store i32 %result, ptr addrspace(1) %out0
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ret void
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}
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; testing extract case with multiple uses
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define amdgpu_kernel void @test_sink_extract_operands(ptr addrspace(1) %ptr, <4 x i32> %input_vec) {
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; OPT-LABEL: define amdgpu_kernel void @test_sink_extract_operands(
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; OPT-SAME: ptr addrspace(1) [[PTR:%.*]], <4 x i32> [[INPUT_VEC:%.*]]) #[[ATTR0]] {
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; OPT-NEXT: [[ENTRY:.*:]]
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; OPT-NEXT: [[VEC_FULL:%.*]] = add <4 x i32> [[INPUT_VEC]], <i32 42, i32 43, i32 44, i32 45>
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; OPT-NEXT: [[EXTRACT0:%.*]] = extractelement <4 x i32> [[VEC_FULL]], i64 0
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; OPT-NEXT: [[VEC_SHIFTED:%.*]] = shl <4 x i32> [[VEC_FULL]], splat (i32 1)
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; OPT-NEXT: [[RESULT0:%.*]] = add i32 [[EXTRACT0]], 100
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; OPT-NEXT: store i32 [[RESULT0]], ptr addrspace(1) [[PTR]], align 4
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; OPT-NEXT: store <4 x i32> [[VEC_SHIFTED]], ptr addrspace(1) [[PTR]], align 16
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; OPT-NEXT: ret void
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;
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entry:
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%vec_full = add <4 x i32> %input_vec, <i32 42, i32 43, i32 44, i32 45>
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%extract0 = extractelement <4 x i32> %vec_full, i64 0
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%vec_shifted = shl <4 x i32> %vec_full, <i32 1, i32 1, i32 1, i32 1>
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%result0 = add i32 %extract0, 100
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store i32 %result0, ptr addrspace(1) %ptr
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store <4 x i32> %vec_shifted, ptr addrspace(1) %ptr
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ret void
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}
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define amdgpu_kernel void @test_shuffle_insert_subvector(ptr addrspace(1) %ptr, <4 x i16> %vec1, <4 x i16> %vec2) {
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; OPT-LABEL: define amdgpu_kernel void @test_shuffle_insert_subvector(
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; OPT-SAME: ptr addrspace(1) [[PTR:%.*]], <4 x i16> [[VEC1:%.*]], <4 x i16> [[VEC2:%.*]]) #[[ATTR0]] {
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; OPT-NEXT: [[ENTRY:.*:]]
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; OPT-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i16> [[VEC1]], <4 x i16> [[VEC2]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
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; OPT-NEXT: [[OTHER_SHUFFLE:%.*]] = shufflevector <4 x i16> [[SHUFFLE]], <4 x i16> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
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; OPT-NEXT: [[RESULT_VEC:%.*]] = add <4 x i16> [[SHUFFLE]], <i16 100, i16 200, i16 300, i16 400>
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; OPT-NEXT: [[OTHER_RESULT:%.*]] = mul <4 x i16> [[OTHER_SHUFFLE]], splat (i16 2)
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; OPT-NEXT: store <4 x i16> [[RESULT_VEC]], ptr addrspace(1) [[PTR]], align 8
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; OPT-NEXT: store <4 x i16> [[OTHER_RESULT]], ptr addrspace(1) [[PTR]], align 8
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; OPT-NEXT: ret void
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;
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entry:
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%shuffle = shufflevector <4 x i16> %vec1, <4 x i16> %vec2, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
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%other_shuffle = shufflevector <4 x i16> %shuffle, <4 x i16> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
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%result_vec = add <4 x i16> %shuffle, <i16 100, i16 200, i16 300, i16 400>
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%other_result = mul <4 x i16> %other_shuffle, <i16 2, i16 2, i16 2, i16 2>
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store <4 x i16> %result_vec, ptr addrspace(1) %ptr
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store <4 x i16> %other_result, ptr addrspace(1) %ptr
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ret void
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}
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define amdgpu_kernel void @test_shuffle_extract_subvector(ptr addrspace(1) %ptr, <4 x i16> %input_vec) {
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; OPT-LABEL: define amdgpu_kernel void @test_shuffle_extract_subvector(
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; OPT-SAME: ptr addrspace(1) [[PTR:%.*]], <4 x i16> [[INPUT_VEC:%.*]]) #[[ATTR0]] {
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; OPT-NEXT: [[ENTRY:.*:]]
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; OPT-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i16> [[INPUT_VEC]], <4 x i16> poison, <2 x i32> <i32 2, i32 3>
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; OPT-NEXT: [[RESULT_VEC:%.*]] = add <2 x i16> [[SHUFFLE]], <i16 100, i16 200>
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; OPT-NEXT: store <2 x i16> [[RESULT_VEC]], ptr addrspace(1) [[PTR]], align 4
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; OPT-NEXT: ret void
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;
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entry:
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%shuffle = shufflevector <4 x i16> %input_vec, <4 x i16> poison, <2 x i32> <i32 2, i32 3>
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%result_vec = add <2 x i16> %shuffle, <i16 100, i16 200>
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store <2 x i16> %result_vec, ptr addrspace(1) %ptr
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ret void
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}
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define amdgpu_kernel void @test_shuffle_sink_operands(ptr addrspace(1) %ptr, <2 x i16> %input_vec) {
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; OPT-LABEL: define amdgpu_kernel void @test_shuffle_sink_operands(
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; OPT-SAME: ptr addrspace(1) [[PTR:%.*]], <2 x i16> [[INPUT_VEC:%.*]]) #[[ATTR0]] {
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; OPT-NEXT: [[ENTRY:.*:]]
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; OPT-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x i16> [[INPUT_VEC]], <2 x i16> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
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; OPT-NEXT: [[RESULT_VEC:%.*]] = add <4 x i16> [[SHUFFLE]], <i16 100, i16 200, i16 300, i16 400>
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; OPT-NEXT: store <4 x i16> [[RESULT_VEC]], ptr addrspace(1) [[PTR]], align 8
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; OPT-NEXT: ret void
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;
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entry:
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%shuffle = shufflevector <2 x i16> %input_vec, <2 x i16> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
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%result_vec = add <4 x i16> %shuffle, <i16 100, i16 200, i16 300, i16 400>
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store <4 x i16> %result_vec, ptr addrspace(1) %ptr
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ret void
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}

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