FPInfo: AMDGPU InstructionSelector

Author: tgymnich

llvm/include/llvm/CodeGen/GlobalISel/Utils.h

@@ -241,13 +241,19 @@ struct DefinitionAndSourceRegister {
 std::optional<DefinitionAndSourceRegister>
 getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI);
 
+std::optional<DefinitionAndSourceRegister>
+getDefSrcRegIgnoringBitcasts(Register Reg, const MachineRegisterInfo &MRI);
+
 /// Find the def instruction for \p Reg, folding away any trivial copies. May
 /// return nullptr if \p Reg is not a generic virtual register.
 ///
 /// Also walks through hints such as G_ASSERT_ZEXT.
 MachineInstr *getDefIgnoringCopies(Register Reg,
                                    const MachineRegisterInfo &MRI);
 
+MachineInstr *getDefIgnoringBitcasts(Register Reg,
+                                     const MachineRegisterInfo &MRI);
+
 /// Find the source register for \p Reg, folding away any trivial copies. It
 /// will be an output register of the instruction that getDefIgnoringCopies
 /// returns. May return an invalid register if \p Reg is not a generic virtual

llvm/lib/CodeGen/GlobalISel/Utils.cpp

@@ -483,6 +483,33 @@ llvm::getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI) {
   return DefinitionAndSourceRegister{DefMI, DefSrcReg};
 }
 
+std::optional<DefinitionAndSourceRegister>
+llvm::getDefSrcRegIgnoringBitcasts(Register Reg, const MachineRegisterInfo &MRI) {
+  Register DefSrcReg = Reg;
+  auto *DefMI = MRI.getVRegDef(Reg);
+  auto DstTy = MRI.getType(DefMI->getOperand(0).getReg());
+  if (!DstTy.isValid())
+    return std::nullopt;
+  unsigned Opc = DefMI->getOpcode();
+  while (Opc == TargetOpcode::G_BITCAST || isPreISelGenericOptimizationHint(Opc)) {
+    Register SrcReg = DefMI->getOperand(1).getReg();
+    auto SrcTy = MRI.getType(SrcReg);
+    if (!SrcTy.isValid())
+      break;
+    DefMI = MRI.getVRegDef(SrcReg);
+    DefSrcReg = SrcReg;
+    Opc = DefMI->getOpcode();
+  }
+  return DefinitionAndSourceRegister{DefMI, DefSrcReg};
+}
+
+MachineInstr *llvm::getDefIgnoringBitcasts(Register Reg,
+  const MachineRegisterInfo &MRI) {
+std::optional<DefinitionAndSourceRegister> DefSrcReg =
+getDefSrcRegIgnoringBitcasts(Reg, MRI);
+return DefSrcReg ? DefSrcReg->MI : nullptr;
+}
+
 MachineInstr *llvm::getDefIgnoringCopies(Register Reg,
                                          const MachineRegisterInfo &MRI) {
   std::optional<DefinitionAndSourceRegister> DefSrcReg =

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

@@ -4282,12 +4282,12 @@ std::pair<Register, unsigned>
 AMDGPUInstructionSelector::selectVOP3PModsImpl(
   Register Src, const MachineRegisterInfo &MRI, bool IsDOT) const {
   unsigned Mods = 0;
-  MachineInstr *MI = MRI.getVRegDef(Src);
+  MachineInstr *MI = getDefIgnoringBitcasts(Src, MRI);
 
   if (MI->getOpcode() == AMDGPU::G_FNEG &&
       // It's possible to see an f32 fneg here, but unlikely.
       // TODO: Treat f32 fneg as only high bit.
-      MRI.getType(Src).isFixedVector(2, 16)) {
+      MRI.getType(MI->getOperand(0).getReg()) == LLT::fixed_vector(2, LLT::float16())) {
     Mods ^= (SISrcMods::NEG | SISrcMods::NEG_HI);
     Src = MI->getOperand(1).getReg();
     MI = MRI.getVRegDef(Src);