[RISCV] Add Zilsd to RISCVMergeBaseOffset.

Author: topperc

llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp

@@ -409,6 +409,7 @@ bool RISCVMergeBaseOffsetOpt::foldIntoMemoryOps(MachineInstr &Hi,
     case RISCV::LHU:
     case RISCV::LWU:
     case RISCV::LD:
+    case RISCV::LD_RV32:
     case RISCV::FLH:
     case RISCV::FLW:
     case RISCV::FLD:
@@ -418,6 +419,7 @@ bool RISCVMergeBaseOffsetOpt::foldIntoMemoryOps(MachineInstr &Hi,
     case RISCV::SW:
     case RISCV::SW_INX:
     case RISCV::SD:
+    case RISCV::SD_RV32:
     case RISCV::FSH:
     case RISCV::FSW:
     case RISCV::FSD: {

llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll

@@ -9,8 +9,7 @@ define double @load_g_0() nounwind {
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:  .Lpcrel_hi0:
 ; CHECK-NEXT:    auipc a0, %pcrel_hi(g_0)
-; CHECK-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi0)
-; CHECK-NEXT:    ld a0, 0(a0)
+; CHECK-NEXT:    ld a0, %pcrel_lo(.Lpcrel_hi0)(a0)
 ; CHECK-NEXT:    ret
 entry:
   %0 = load double, ptr @g_0
@@ -22,9 +21,8 @@ define void @store_g_0() nounwind {
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:  .Lpcrel_hi1:
 ; CHECK-NEXT:    auipc a0, %pcrel_hi(g_0)
-; CHECK-NEXT:    addi a0, a0, %pcrel_lo(.Lpcrel_hi1)
 ; CHECK-NEXT:    fcvt.d.w a2, zero
-; CHECK-NEXT:    sd a2, 0(a0)
+; CHECK-NEXT:    sd a2, %pcrel_lo(.Lpcrel_hi1)(a0)
 ; CHECK-NEXT:    ret
 entry:
   store double 0.0, ptr @g_0