Add new opcode for rounding to odd

Author: HolyMolyCowMan

llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

@@ -1332,6 +1332,20 @@ class LLVM_ABI MachineIRBuilder {
   buildFPTrunc(const DstOp &Res, const SrcOp &Op,
                std::optional<unsigned> Flags = std::nullopt);
 
+  /// Build and insert \p Res = G_FPTRUNC_ODD \p Op
+  ///
+  /// G_FPTRUNC_ODD converts a floating-point value into one with a smaller type using round to odd.
+  ///
+  /// \pre setBasicBlock or setMI must have been called.
+  /// \pre \p Res must be a generic virtual register with scalar or vector type.
+  /// \pre \p Op must be a generic virtual register with scalar or vector type.
+  /// \pre \p Res must be smaller than \p Op
+  ///
+  /// \return The newly created instruction.
+  MachineInstrBuilder
+  buildFPTruncOdd(const DstOp &Res, const SrcOp &Op,
+               std::optional<unsigned> Flags = std::nullopt);
+
   /// Build and insert \p Res = G_TRUNC \p Op
   ///
   /// G_TRUNC extracts the low bits of a type. For a vector type each element is

llvm/include/llvm/Support/TargetOpcodes.def

@@ -692,6 +692,9 @@ HANDLE_TARGET_OPCODE(G_FPEXT)
 /// Generic float to signed-int conversion
 HANDLE_TARGET_OPCODE(G_FPTRUNC)
 
+/// Generic float to signed-int conversion using round to odd
+HANDLE_TARGET_OPCODE(G_FPTRUNC_ODD)
+
 /// Generic float to signed-int conversion
 HANDLE_TARGET_OPCODE(G_FPTOSI)
 

llvm/include/llvm/Target/GenericOpcodes.td

@@ -782,6 +782,12 @@ def G_FPTRUNC : GenericInstruction {
   let hasSideEffects = false;
 }
 
+def G_FPTRUNC_ODD : GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type1:$src);
+  let hasSideEffects = false;
+}
+
 def G_FPTOSI : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type1:$src);

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

@@ -5595,6 +5595,7 @@ LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
   case G_ANYEXT:
   case G_FPEXT:
   case G_FPTRUNC:
+  case G_FPTRUNC_ODD:
   case G_SITOFP:
   case G_UITOFP:
   case G_FPTOSI:

llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

@@ -936,6 +936,12 @@ MachineIRBuilder::buildFPTrunc(const DstOp &Res, const SrcOp &Op,
   return buildInstr(TargetOpcode::G_FPTRUNC, Res, Op, Flags);
 }
 
+MachineInstrBuilder
+MachineIRBuilder::buildFPTruncOdd(const DstOp &Res, const SrcOp &Op,
+                               std::optional<unsigned> Flags) {
+  return buildInstr(TargetOpcode::G_FPTRUNC_ODD, Res, Op, Flags);
+}
+
 MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred,
                                                 const DstOp &Res,
                                                 const SrcOp &Op0,

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

@@ -831,6 +831,11 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
       .clampNumElements(1, v2s64, v2s64)
       .scalarize(0);
 
+  getActionDefinitionsBuilder(G_FPTRUNC_ODD)
+    .legalFor({{s16, s32}, {s32, s64}, {v4s16, v4s32}, {v2s32, v2s64}})
+    .clampMaxNumElements(1, s32, 4)
+    .clampMaxNumElements(1, s64, 2);
+
   getActionDefinitionsBuilder(G_FPEXT)
       .legalFor(
           {{s32, s16}, {s64, s16}, {s64, s32}, {v4s32, v4s16}, {v2s64, v2s32}})
@@ -2422,7 +2427,7 @@ bool AArch64LegalizerInfo::legalizeFptrunc(
   default:
     return false;
   case TargetOpcode::G_FPTRUNC: {
-    Mid = MIRBuilder.buildFPTrunc(MidTy, Src);
+    Mid = MIRBuilder.buildFPTruncOdd(MidTy, Src);
     Fin = MIRBuilder.buildFPTrunc(DstTy, Mid.getReg(0));
     break;
   }