- Remove unused references to FORM_STRIDED_TUPLE

- Removed switch from getRegAllocationHints

Author: kmclaughlin-arm

llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

@@ -504,8 +504,6 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
 
   bool SelectAllActivePredicate(SDValue N);
   bool SelectAnyPredicate(SDValue N);
-
-  void SelectFormTuplePseudo(SDNode *N);
 };
 
 class AArch64DAGToDAGISelLegacy : public SelectionDAGISelLegacy {

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -2808,8 +2808,6 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
     MAKE_CASE(AArch64ISD::FMUL_PRED)
     MAKE_CASE(AArch64ISD::FSUB_PRED)
     MAKE_CASE(AArch64ISD::RDSVL)
-    MAKE_CASE(AArch64ISD::FORM_STRIDED_TUPLE_X2)
-    MAKE_CASE(AArch64ISD::FORM_STRIDED_TUPLE_X4)
     MAKE_CASE(AArch64ISD::BIC)
     MAKE_CASE(AArch64ISD::CBZ)
     MAKE_CASE(AArch64ISD::CBNZ)

llvm/lib/Target/AArch64/AArch64ISelLowering.h

@@ -478,9 +478,6 @@ enum NodeType : unsigned {
   SME_ZA_LDR,
   SME_ZA_STR,
 
-  FORM_STRIDED_TUPLE_X2,
-  FORM_STRIDED_TUPLE_X4,
-
   // NEON Load/Store with post-increment base updates
   LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE,
   LD3post,

llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

@@ -1144,26 +1144,14 @@ bool AArch64RegisterInfo::getRegAllocationHints(
     if (!VRM->hasPhys(FirstLoadVirtReg))
       continue;
 
-    unsigned SubRegIdx = 0;
+    int64_t SubRegIdx = -1;
     MCRegister FirstLoadPhysReg = VRM->getPhys(FirstLoadVirtReg);
 
     // The subreg number is used to access the correct unit of the
     // strided register found in the map above.
-    switch (MI.getOperand(1).getSubReg()) {
-    case AArch64::zsub0:
-      break;
-    case AArch64::zsub1:
-      SubRegIdx = 1;
-      break;
-    case AArch64::zsub2:
-      SubRegIdx = 2;
-      break;
-    case AArch64::zsub3:
-      SubRegIdx = 3;
-      break;
-    default:
+    SubRegIdx = MI.getOperand(1).getSubReg() - AArch64::zsub0;
+    if (SubRegIdx < 0 || SubRegIdx > 3)
       continue;
-    }
 
     SmallVector<Register, 4> RegUnits;
     for (MCRegUnit Unit : TRI->regunits(FirstLoadPhysReg))

llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

@@ -29,16 +29,6 @@ def AArch64_save_zt : SDNode<"AArch64ISD::SAVE_ZT", SDTypeProfile<0, 2,
                              [SDTCisInt<0>, SDTCisPtrTy<1>]>,
                              [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>;
 
-def SDT_FORM_STRIDED_TUPLE_X2 : SDTypeProfile<2, 2,
-                             [SDTCisVec<0>, SDTCisSameAs<0, 1>,
-                              SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>]>;
-
-def SDT_FORM_STRIDED_TUPLE_X4 : SDTypeProfile<4, 4,
-                             [SDTCisVec<0>, SDTCisSameAs<0, 1>,
-                              SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
-                              SDTCisSameAs<0, 4>, SDTCisSameAs<0, 5>,
-                              SDTCisSameAs<0, 6>, SDTCisSameAs<0, 7>]>;
-
 def AArch64CoalescerBarrier
     : SDNode<"AArch64ISD::COALESCER_BARRIER", SDTypeProfile<1, 1, []>, [SDNPOptInGlue, SDNPOutGlue]>;