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[AMDGPU] Add GFX12 wave register names with WAVE_ prefix
Rename canonical register names with WAVE_ prefix for GFX12 - Maintain backward compatibility through aliases
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5 files changed

+124
-67
lines changed

5 files changed

+124
-67
lines changed

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp‎

Lines changed: 30 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -169,7 +169,14 @@ namespace Hwreg {
169169
// NOLINTBEGIN
170170
// clang-format off
171171
static constexpr CustomOperand Operands[] = {
172-
{{""}},
172+
// GFX12+ renamed registers
173+
{{"HW_REG_WAVE_MODE"}, ID_MODE, isGFX12Plus},
174+
{{"HW_REG_WAVE_STATUS"}, ID_STATUS, isGFX12Plus},
175+
{{"HW_REG_WAVE_GPR_ALLOC"}, ID_GPR_ALLOC, isGFX12Plus},
176+
{{"HW_REG_WAVE_LDS_ALLOC"}, ID_LDS_ALLOC, isGFX12Plus},
177+
{{"HW_REG_WAVE_HW_ID1"}, ID_HW_ID1, isGFX12Plus},
178+
{{"HW_REG_WAVE_HW_ID2"}, ID_HW_ID2, isGFX12Plus},
179+
173180
{{"HW_REG_MODE"}, ID_MODE},
174181
{{"HW_REG_STATUS"}, ID_STATUS},
175182
{{"HW_REG_TRAPSTS"}, ID_TRAPSTS, isNotGFX12Plus},
@@ -198,25 +205,25 @@ static constexpr CustomOperand Operands[] = {
198205
{{""}},
199206
{{"HW_REG_PERF_SNAPSHOT_DATA"}, ID_PERF_SNAPSHOT_DATA_gfx11, isGFX11},
200207
{{"HW_REG_IB_STS2"}, ID_IB_STS2, isGFX1250},
201-
{{"HW_REG_SHADER_CYCLES"}, ID_SHADER_CYCLES, isGFX10_3_GFX11},
202-
{{"HW_REG_SHADER_CYCLES_HI"}, ID_SHADER_CYCLES_HI, isGFX12Plus},
203-
{{"HW_REG_DVGPR_ALLOC_LO"}, ID_DVGPR_ALLOC_LO, isGFX12Plus},
204-
{{"HW_REG_DVGPR_ALLOC_HI"}, ID_DVGPR_ALLOC_HI, isGFX12Plus},
208+
{{"HW_REG_SHADER_CYCLES"}, ID_SHADER_CYCLES, isGFX10_3_GFX11},
209+
{{"HW_REG_SHADER_CYCLES_HI"}, ID_SHADER_CYCLES_HI, isGFX12Plus},
210+
{{"HW_REG_WAVE_DVGPR_ALLOC_LO"}, ID_DVGPR_ALLOC_LO, isGFX12Plus},
211+
{{"HW_REG_WAVE_DVGPR_ALLOC_HI"}, ID_DVGPR_ALLOC_HI, isGFX12Plus},
205212

206213
// Register numbers reused in GFX11
207214
{{"HW_REG_PERF_SNAPSHOT_PC_LO"}, ID_PERF_SNAPSHOT_PC_LO_gfx11, isGFX11},
208215
{{"HW_REG_PERF_SNAPSHOT_PC_HI"}, ID_PERF_SNAPSHOT_PC_HI_gfx11, isGFX11},
209216

210217
// Register numbers reused in GFX12+
211-
{{"HW_REG_STATE_PRIV"}, ID_STATE_PRIV, isGFX12Plus},
212-
{{"HW_REG_PERF_SNAPSHOT_DATA1"}, ID_PERF_SNAPSHOT_DATA1, isGFX12Plus},
213-
{{"HW_REG_PERF_SNAPSHOT_DATA2"}, ID_PERF_SNAPSHOT_DATA2, isGFX12Plus},
214-
{{"HW_REG_EXCP_FLAG_PRIV"}, ID_EXCP_FLAG_PRIV, isGFX12Plus},
215-
{{"HW_REG_EXCP_FLAG_USER"}, ID_EXCP_FLAG_USER, isGFX12Plus},
216-
{{"HW_REG_TRAP_CTRL"}, ID_TRAP_CTRL, isGFX12Plus},
217-
{{"HW_REG_SCRATCH_BASE_LO"}, ID_FLAT_SCR_LO, isGFX12Plus},
218-
{{"HW_REG_SCRATCH_BASE_HI"}, ID_FLAT_SCR_HI, isGFX12Plus},
219-
{{"HW_REG_SHADER_CYCLES_LO"}, ID_SHADER_CYCLES, isGFX12Plus},
218+
{{"HW_REG_WAVE_STATE_PRIV"}, ID_STATE_PRIV, isGFX12Plus},
219+
{{"HW_REG_PERF_SNAPSHOT_DATA1"}, ID_PERF_SNAPSHOT_DATA1, isGFX12Plus},
220+
{{"HW_REG_PERF_SNAPSHOT_DATA2"}, ID_PERF_SNAPSHOT_DATA2, isGFX12Plus},
221+
{{"HW_REG_WAVE_EXCP_FLAG_PRIV"}, ID_EXCP_FLAG_PRIV, isGFX12Plus},
222+
{{"HW_REG_WAVE_EXCP_FLAG_USER"}, ID_EXCP_FLAG_USER, isGFX12Plus},
223+
{{"HW_REG_WAVE_TRAP_CTRL"}, ID_TRAP_CTRL, isGFX12Plus},
224+
{{"HW_REG_WAVE_SCRATCH_BASE_LO"}, ID_FLAT_SCR_LO, isGFX12Plus},
225+
{{"HW_REG_WAVE_SCRATCH_BASE_HI"}, ID_FLAT_SCR_HI, isGFX12Plus},
226+
{{"HW_REG_SHADER_CYCLES_LO"}, ID_SHADER_CYCLES, isGFX12Plus},
220227

221228
// GFX942 specific registers
222229
{{"HW_REG_XCC_ID"}, ID_XCC_ID, isGFX940},
@@ -230,7 +237,15 @@ static constexpr CustomOperand Operands[] = {
230237
{{"HW_REG_XNACK_MASK"}, ID_XNACK_MASK_gfx1250, isGFX1250},
231238

232239
// Aliases
233-
{{"HW_REG_HW_ID"}, ID_HW_ID1, isGFX10},
240+
{{"HW_REG_HW_ID"}, ID_HW_ID1, isGFX10},
241+
{{"HW_REG_STATE_PRIV"}, ID_STATE_PRIV, isGFX12Plus},
242+
{{"HW_REG_EXCP_FLAG_PRIV"}, ID_EXCP_FLAG_PRIV, isGFX12Plus},
243+
{{"HW_REG_EXCP_FLAG_USER"}, ID_EXCP_FLAG_USER, isGFX12Plus},
244+
{{"HW_REG_TRAP_CTRL"}, ID_TRAP_CTRL, isGFX12Plus},
245+
{{"HW_REG_SCRATCH_BASE_LO"}, ID_FLAT_SCR_LO, isGFX12Plus},
246+
{{"HW_REG_SCRATCH_BASE_HI"}, ID_FLAT_SCR_HI, isGFX12Plus},
247+
{{"HW_REG_DVGPR_ALLOC_LO"}, ID_DVGPR_ALLOC_LO, isGFX12Plus},
248+
{{"HW_REG_DVGPR_ALLOC_HI"}, ID_DVGPR_ALLOC_HI, isGFX12Plus},
234249
};
235250
// clang-format on
236251
// NOLINTEND

‎llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
define amdgpu_cs void @amdgpu_cs() #0 {
88
; CHECK-LABEL: amdgpu_cs:
99
; CHECK: ; %bb.0:
10-
; CHECK-NEXT: s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
10+
; CHECK-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
1111
; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
1212
; CHECK-NEXT: s_cmp_lg_u32 0, s33
1313
; CHECK-NEXT: s_cmovk_i32 s33, 0x1c0
@@ -19,7 +19,7 @@ define amdgpu_cs void @amdgpu_cs() #0 {
1919
define amdgpu_kernel void @kernel() #0 {
2020
; CHECK-LABEL: kernel:
2121
; CHECK: ; %bb.0:
22-
; CHECK-NEXT: s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
22+
; CHECK-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
2323
; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
2424
; CHECK-NEXT: s_cmp_lg_u32 0, s33
2525
; CHECK-NEXT: s_cmovk_i32 s33, 0x1c0
@@ -31,7 +31,7 @@ define amdgpu_kernel void @kernel() #0 {
3131
define amdgpu_cs void @with_local() #0 {
3232
; CHECK-TRUE16-LABEL: with_local:
3333
; CHECK-TRUE16: ; %bb.0:
34-
; CHECK-TRUE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
34+
; CHECK-TRUE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
3535
; CHECK-TRUE16-NEXT: v_mov_b16_e32 v0.l, 13
3636
; CHECK-TRUE16-NEXT: s_cmp_lg_u32 0, s33
3737
; CHECK-TRUE16-NEXT: s_cmovk_i32 s33, 0x1c0
@@ -42,7 +42,7 @@ define amdgpu_cs void @with_local() #0 {
4242
;
4343
; CHECK-FAKE16-LABEL: with_local:
4444
; CHECK-FAKE16: ; %bb.0:
45-
; CHECK-FAKE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
45+
; CHECK-FAKE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
4646
; CHECK-FAKE16-NEXT: v_mov_b32_e32 v0, 13
4747
; CHECK-FAKE16-NEXT: s_cmp_lg_u32 0, s33
4848
; CHECK-FAKE16-NEXT: s_cmovk_i32 s33, 0x1c0
@@ -60,7 +60,7 @@ define amdgpu_cs void @with_local() #0 {
6060
define amdgpu_cs void @with_calls_inline_const() #0 {
6161
; CHECK-TRUE16-LABEL: with_calls_inline_const:
6262
; CHECK-TRUE16: ; %bb.0:
63-
; CHECK-TRUE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
63+
; CHECK-TRUE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
6464
; CHECK-TRUE16-NEXT: v_mov_b16_e32 v0.l, 15
6565
; CHECK-TRUE16-NEXT: s_cmp_lg_u32 0, s33
6666
; CHECK-TRUE16-NEXT: s_mov_b32 s1, callee@abs32@hi
@@ -76,7 +76,7 @@ define amdgpu_cs void @with_calls_inline_const() #0 {
7676
;
7777
; CHECK-FAKE16-LABEL: with_calls_inline_const:
7878
; CHECK-FAKE16: ; %bb.0:
79-
; CHECK-FAKE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
79+
; CHECK-FAKE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
8080
; CHECK-FAKE16-NEXT: v_mov_b32_e32 v0, 15
8181
; CHECK-FAKE16-NEXT: s_cmp_lg_u32 0, s33
8282
; CHECK-FAKE16-NEXT: s_mov_b32 s1, callee@abs32@hi
@@ -100,7 +100,7 @@ define amdgpu_cs void @with_calls_inline_const() #0 {
100100
define amdgpu_cs void @with_calls_no_inline_const() #0 {
101101
; CHECK-TRUE16-LABEL: with_calls_no_inline_const:
102102
; CHECK-TRUE16: ; %bb.0:
103-
; CHECK-TRUE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
103+
; CHECK-TRUE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
104104
; CHECK-TRUE16-NEXT: v_mov_b16_e32 v0.l, 15
105105
; CHECK-TRUE16-NEXT: s_cmp_lg_u32 0, s33
106106
; CHECK-TRUE16-NEXT: s_mov_b32 s1, callee@abs32@hi
@@ -117,7 +117,7 @@ define amdgpu_cs void @with_calls_no_inline_const() #0 {
117117
;
118118
; CHECK-FAKE16-LABEL: with_calls_no_inline_const:
119119
; CHECK-FAKE16: ; %bb.0:
120-
; CHECK-FAKE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
120+
; CHECK-FAKE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
121121
; CHECK-FAKE16-NEXT: v_mov_b32_e32 v0, 15
122122
; CHECK-FAKE16-NEXT: s_cmp_lg_u32 0, s33
123123
; CHECK-FAKE16-NEXT: s_mov_b32 s1, callee@abs32@hi
@@ -140,7 +140,7 @@ define amdgpu_cs void @with_calls_no_inline_const() #0 {
140140
define amdgpu_cs void @with_spills() #0 {
141141
; CHECK-LABEL: with_spills:
142142
; CHECK: ; %bb.0:
143-
; CHECK-NEXT: s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
143+
; CHECK-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
144144
; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
145145
; CHECK-NEXT: s_cmp_lg_u32 0, s33
146146
; CHECK-NEXT: s_cmovk_i32 s33, 0x1c0
@@ -153,7 +153,7 @@ define amdgpu_cs void @with_spills() #0 {
153153
define amdgpu_cs void @realign_stack(<32 x i32> %x) #0 {
154154
; CHECK-LABEL: realign_stack:
155155
; CHECK: ; %bb.0:
156-
; CHECK-NEXT: s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
156+
; CHECK-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
157157
; CHECK-NEXT: v_mov_b32_e32 v32, 0
158158
; CHECK-NEXT: s_cmp_lg_u32 0, s33
159159
; CHECK-NEXT: s_mov_b32 s1, callee@abs32@hi
@@ -187,7 +187,7 @@ define amdgpu_cs void @realign_stack(<32 x i32> %x) #0 {
187187
define amdgpu_cs void @frame_pointer_none() #1 {
188188
; CHECK-TRUE16-LABEL: frame_pointer_none:
189189
; CHECK-TRUE16: ; %bb.0:
190-
; CHECK-TRUE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
190+
; CHECK-TRUE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
191191
; CHECK-TRUE16-NEXT: v_mov_b16_e32 v0.l, 13
192192
; CHECK-TRUE16-NEXT: s_cmp_lg_u32 0, s33
193193
; CHECK-TRUE16-NEXT: s_cmovk_i32 s33, 0x1c0
@@ -198,7 +198,7 @@ define amdgpu_cs void @frame_pointer_none() #1 {
198198
;
199199
; CHECK-FAKE16-LABEL: frame_pointer_none:
200200
; CHECK-FAKE16: ; %bb.0:
201-
; CHECK-FAKE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
201+
; CHECK-FAKE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
202202
; CHECK-FAKE16-NEXT: v_mov_b32_e32 v0, 13
203203
; CHECK-FAKE16-NEXT: s_cmp_lg_u32 0, s33
204204
; CHECK-FAKE16-NEXT: s_cmovk_i32 s33, 0x1c0
@@ -214,7 +214,7 @@ define amdgpu_cs void @frame_pointer_none() #1 {
214214
define amdgpu_cs void @frame_pointer_all() #2 {
215215
; CHECK-TRUE16-LABEL: frame_pointer_all:
216216
; CHECK-TRUE16: ; %bb.0:
217-
; CHECK-TRUE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
217+
; CHECK-TRUE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
218218
; CHECK-TRUE16-NEXT: v_mov_b16_e32 v0.l, 13
219219
; CHECK-TRUE16-NEXT: s_cmp_lg_u32 0, s33
220220
; CHECK-TRUE16-NEXT: s_cmovk_i32 s33, 0x1c0
@@ -225,7 +225,7 @@ define amdgpu_cs void @frame_pointer_all() #2 {
225225
;
226226
; CHECK-FAKE16-LABEL: frame_pointer_all:
227227
; CHECK-FAKE16: ; %bb.0:
228-
; CHECK-FAKE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
228+
; CHECK-FAKE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
229229
; CHECK-FAKE16-NEXT: v_mov_b32_e32 v0, 13
230230
; CHECK-FAKE16-NEXT: s_cmp_lg_u32 0, s33
231231
; CHECK-FAKE16-NEXT: s_cmovk_i32 s33, 0x1c0

‎llvm/test/MC/AMDGPU/gfx12_asm_sopk.s‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -193,19 +193,19 @@ s_call_b64 vcc, 0x1234
193193
s_call_b64 null, 0x1234
194194
// GFX12: encoding: [0x34,0x12,0x7c,0xba]
195195

196-
s_getreg_b32 s0, hwreg(HW_REG_MODE)
196+
s_getreg_b32 s0, hwreg(HW_REG_WAVE_MODE)
197197
// GFX12: encoding: [0x01,0xf8,0x80,0xb8]
198198

199-
s_getreg_b32 s0, hwreg(HW_REG_STATUS)
199+
s_getreg_b32 s0, hwreg(HW_REG_WAVE_STATUS)
200200
// GFX12: encoding: [0x02,0xf8,0x80,0xb8]
201201

202-
s_getreg_b32 s0, hwreg(HW_REG_STATE_PRIV)
202+
s_getreg_b32 s0, hwreg(HW_REG_WAVE_STATE_PRIV)
203203
// GFX12: encoding: [0x04,0xf8,0x80,0xb8]
204204

205-
s_getreg_b32 s0, hwreg(HW_REG_GPR_ALLOC)
205+
s_getreg_b32 s0, hwreg(HW_REG_WAVE_GPR_ALLOC)
206206
// GFX12: encoding: [0x05,0xf8,0x80,0xb8]
207207

208-
s_getreg_b32 s0, hwreg(HW_REG_LDS_ALLOC)
208+
s_getreg_b32 s0, hwreg(HW_REG_WAVE_LDS_ALLOC)
209209
// GFX12: encoding: [0x06,0xf8,0x80,0xb8]
210210

211211
s_getreg_b32 s0, hwreg(HW_REG_IB_STS)
@@ -226,31 +226,31 @@ s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_DATA1)
226226
s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_DATA2)
227227
// GFX12: encoding: [0x10,0xf8,0x80,0xb8]
228228

229-
s_getreg_b32 s0, hwreg(HW_REG_EXCP_FLAG_PRIV)
229+
s_getreg_b32 s0, hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV)
230230
// GFX12: encoding: [0x11,0xf8,0x80,0xb8]
231231

232-
s_getreg_b32 s0, hwreg(HW_REG_EXCP_FLAG_USER)
232+
s_getreg_b32 s0, hwreg(HW_REG_WAVE_EXCP_FLAG_USER)
233233
// GFX12: encoding: [0x12,0xf8,0x80,0xb8]
234234

235-
s_getreg_b32 s0, hwreg(HW_REG_TRAP_CTRL)
235+
s_getreg_b32 s0, hwreg(HW_REG_WAVE_TRAP_CTRL)
236236
// GFX12: encoding: [0x13,0xf8,0x80,0xb8]
237237

238-
s_getreg_b32 s0, hwreg(HW_REG_SCRATCH_BASE_LO)
238+
s_getreg_b32 s0, hwreg(HW_REG_WAVE_SCRATCH_BASE_LO)
239239
// GFX12: encoding: [0x14,0xf8,0x80,0xb8]
240240

241-
s_getreg_b32 s0, hwreg(HW_REG_SCRATCH_BASE_HI)
241+
s_getreg_b32 s0, hwreg(HW_REG_WAVE_SCRATCH_BASE_HI)
242242
// GFX12: encoding: [0x15,0xf8,0x80,0xb8]
243243

244-
s_getreg_b32 s0, hwreg(HW_REG_HW_ID1)
244+
s_getreg_b32 s0, hwreg(HW_REG_WAVE_HW_ID1)
245245
// GFX12: encoding: [0x17,0xf8,0x80,0xb8]
246246

247-
s_getreg_b32 s0, hwreg(HW_REG_HW_ID2)
247+
s_getreg_b32 s0, hwreg(HW_REG_WAVE_HW_ID2)
248248
// GFX12: encoding: [0x18,0xf8,0x80,0xb8]
249249

250-
s_getreg_b32 s0, hwreg(HW_REG_DVGPR_ALLOC_LO)
250+
s_getreg_b32 s0, hwreg(HW_REG_WAVE_DVGPR_ALLOC_LO)
251251
// GFX12: encoding: [0x1f,0xf8,0x80,0xb8]
252252

253-
s_getreg_b32 s0, hwreg(HW_REG_DVGPR_ALLOC_HI)
253+
s_getreg_b32 s0, hwreg(HW_REG_WAVE_DVGPR_ALLOC_HI)
254254
// GFX12: encoding: [0x20,0xf8,0x80,0xb8]
255255

256256
s_getreg_b32 s0, hwreg(HW_REG_SHADER_CYCLES_LO)

‎llvm/test/MC/AMDGPU/gfx12_asm_sopk_alias.s‎

Lines changed: 43 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,46 @@
11
// RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1200 %s | FileCheck --check-prefix=GFX12 %s
22

33
s_addk_i32 s0, 0x1234
4-
// GFX12: s_addk_co_i32 s0, 0x1234 ; encoding: [0x34,0x12,0x80,0xb7]
4+
// GFX12: s_addk_co_i32 s0, 0x1234 ; encoding: [0x34,0x12,0x80,0xb7]
5+
6+
s_getreg_b32 s0, hwreg(HW_REG_MODE)
7+
// GFX12: s_getreg_b32 s0, hwreg(HW_REG_WAVE_MODE) ; encoding: [0x01,0xf8,0x80,0xb8]
8+
9+
s_getreg_b32 s0, hwreg(HW_REG_STATUS)
10+
// GFX12: s_getreg_b32 s0, hwreg(HW_REG_WAVE_STATUS) ; encoding: [0x02,0xf8,0x80,0xb8]
11+
12+
s_getreg_b32 s0, hwreg(HW_REG_STATE_PRIV)
13+
// GFX12: s_getreg_b32 s0, hwreg(HW_REG_WAVE_STATE_PRIV) ; encoding: [0x04,0xf8,0x80,0xb8]
14+
15+
s_getreg_b32 s0, hwreg(HW_REG_GPR_ALLOC)
16+
// GFX12: s_getreg_b32 s0, hwreg(HW_REG_WAVE_GPR_ALLOC) ; encoding: [0x05,0xf8,0x80,0xb8]
17+
18+
s_getreg_b32 s0, hwreg(HW_REG_LDS_ALLOC)
19+
// GFX12: s_getreg_b32 s0, hwreg(HW_REG_WAVE_LDS_ALLOC) ; encoding: [0x06,0xf8,0x80,0xb8]
20+
21+
s_getreg_b32 s0, hwreg(HW_REG_EXCP_FLAG_PRIV)
22+
// GFX12: s_getreg_b32 s0, hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV) ; encoding: [0x11,0xf8,0x80,0xb8]
23+
24+
s_getreg_b32 s0, hwreg(HW_REG_EXCP_FLAG_USER)
25+
// GFX12: s_getreg_b32 s0, hwreg(HW_REG_WAVE_EXCP_FLAG_USER) ; encoding: [0x12,0xf8,0x80,0xb8]
26+
27+
s_getreg_b32 s0, hwreg(HW_REG_TRAP_CTRL)
28+
// GFX12: s_getreg_b32 s0, hwreg(HW_REG_WAVE_TRAP_CTRL) ; encoding: [0x13,0xf8,0x80,0xb8]
29+
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s_getreg_b32 s0, hwreg(HW_REG_SCRATCH_BASE_LO)
31+
// GFX12: s_getreg_b32 s0, hwreg(HW_REG_WAVE_SCRATCH_BASE_LO) ; encoding: [0x14,0xf8,0x80,0xb8]
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s_getreg_b32 s0, hwreg(HW_REG_SCRATCH_BASE_HI)
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// GFX12: s_getreg_b32 s0, hwreg(HW_REG_WAVE_SCRATCH_BASE_HI) ; encoding: [0x15,0xf8,0x80,0xb8]
35+
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s_getreg_b32 s0, hwreg(HW_REG_HW_ID1)
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// GFX12: s_getreg_b32 s0, hwreg(HW_REG_WAVE_HW_ID1) ; encoding: [0x17,0xf8,0x80,0xb8]
38+
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s_getreg_b32 s0, hwreg(HW_REG_HW_ID2)
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// GFX12: s_getreg_b32 s0, hwreg(HW_REG_WAVE_HW_ID2) ; encoding: [0x18,0xf8,0x80,0xb8]
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s_getreg_b32 s0, hwreg(HW_REG_DVGPR_ALLOC_LO)
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// GFX12: s_getreg_b32 s0, hwreg(HW_REG_WAVE_DVGPR_ALLOC_LO) ; encoding: [0x1f,0xf8,0x80,0xb8]
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s_getreg_b32 s0, hwreg(HW_REG_DVGPR_ALLOC_HI)
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// GFX12: s_getreg_b32 s0, hwreg(HW_REG_WAVE_DVGPR_ALLOC_HI) ; encoding: [0x20,0xf8,0x80,0xb8]

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