Fix issue 50142 by adding AnyTrueCombine

This introduces the fold (any_true (setcc <X> 0, eq)) to (not
(all_true)), allowing potential extra fold of (not (not ...))

Introduces test simd-setcc-reductions and readjusts simd-vecreduce-bool

Author: badumbatish

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

@@ -3239,6 +3239,42 @@ static SDValue performBitcastCombine(SDNode *N,
   return SDValue();
 }
 
+static SDValue performAnyTrueCombine(SDNode *N, SelectionDAG &DAG) {
+  // any_true (setcc <X>, 0, eq)
+  // => not (all_true X)
+
+  SDLoc DL(N);
+  assert(N->getOpcode() == ISD::INTRINSIC_WO_CHAIN);
+  if (N->getConstantOperandVal(0) != Intrinsic::wasm_anytrue)
+    return SDValue();
+
+  SDValue SetCC = N->getOperand(1);
+  if (SetCC.getOpcode() != ISD::SETCC)
+    return SDValue();
+
+  SDValue LHS = SetCC->getOperand(0);
+  SDValue RHS = SetCC->getOperand(1);
+  ISD::CondCode Cond = cast<CondCodeSDNode>(SetCC->getOperand(2))->get();
+  EVT LT = LHS.getValueType();
+  unsigned NumElts = LT.getVectorNumElements();
+  if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
+    return SDValue();
+
+  EVT Width = MVT::getIntegerVT(128 / NumElts);
+
+  if (!isNullOrNullSplat(RHS) || Cond != ISD::SETEQ)
+    return SDValue();
+
+  SDValue Ret = DAG.getZExtOrTrunc(
+      DAG.getNode(
+          ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
+          {DAG.getConstant(Intrinsic::wasm_alltrue, DL, MVT::i32),
+           DAG.getSExtOrTrunc(LHS, DL, LT.changeVectorElementType(Width))}),
+      DL, MVT::i1);
+  Ret = DAG.getNOT(DL, Ret, MVT::i1);
+  return DAG.getZExtOrTrunc(Ret, DL, N->getValueType(0));
+}
+
 template <int MatchRHS, ISD::CondCode MatchCond, bool RequiresNegate,
           Intrinsic::ID Intrin>
 static SDValue TryMatchTrue(SDNode *N, EVT VecVT, SelectionDAG &DAG) {
@@ -3427,8 +3463,11 @@ WebAssemblyTargetLowering::PerformDAGCombine(SDNode *N,
     return performVectorTruncZeroCombine(N, DCI);
   case ISD::TRUNCATE:
     return performTruncateCombine(N, DCI);
-  case ISD::INTRINSIC_WO_CHAIN:
+  case ISD::INTRINSIC_WO_CHAIN: {
+    if (auto AnyTrueCombine = performAnyTrueCombine(N, DCI.DAG))
+      return AnyTrueCombine;
     return performLowerPartialReduction(N, DCI.DAG);
+  }
   case ISD::MUL:
     return performMulCombine(N, DCI.DAG);
   }

llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll

@@ -7,14 +7,8 @@ define i32 @all_true_16_i8(<16 x i8> %v) {
 ; CHECK-LABEL: all_true_16_i8:
 ; CHECK:         .functype all_true_16_i8 (v128) -> (i32)
 ; CHECK-NEXT:  # %bb.0:
-; CHECK-NEXT:    v128.const $push0=, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
-; CHECK-NEXT:    i8x16.eq $push1=, $0, $pop0
-; CHECK-NEXT:    v128.any_true $push2=, $pop1
-; CHECK-NEXT:    i32.const $push3=, -1
-; CHECK-NEXT:    i32.xor $push4=, $pop2, $pop3
-; CHECK-NEXT:    i32.const $push5=, 1
-; CHECK-NEXT:    i32.and $push6=, $pop4, $pop5
-; CHECK-NEXT:    return $pop6
+; CHECK-NEXT:    i8x16.all_true $push0=, $0
+; CHECK-NEXT:    return $pop0
   %1 = icmp eq <16 x i8> %v, zeroinitializer
   %2 = bitcast <16 x i1> %1 to i16
   %3 = icmp eq i16 %2, 0
@@ -27,14 +21,8 @@ define i32 @all_true_4_i32(<4 x i32> %v) {
 ; CHECK-LABEL: all_true_4_i32:
 ; CHECK:         .functype all_true_4_i32 (v128) -> (i32)
 ; CHECK-NEXT:  # %bb.0:
-; CHECK-NEXT:    v128.const $push0=, 0, 0, 0, 0
-; CHECK-NEXT:    i32x4.eq $push1=, $0, $pop0
-; CHECK-NEXT:    v128.any_true $push2=, $pop1
-; CHECK-NEXT:    i32.const $push3=, -1
-; CHECK-NEXT:    i32.xor $push4=, $pop2, $pop3
-; CHECK-NEXT:    i32.const $push5=, 1
-; CHECK-NEXT:    i32.and $push6=, $pop4, $pop5
-; CHECK-NEXT:    return $pop6
+; CHECK-NEXT:    i32x4.all_true $push0=, $0
+; CHECK-NEXT:    return $pop0
   %1 = icmp eq <4 x i32> %v, zeroinitializer
   %2 = bitcast <4 x i1> %1 to i4
   %3 = icmp eq i4 %2, 0
@@ -47,14 +35,8 @@ define i32 @all_true_8_i16(<8 x i16> %v) {
 ; CHECK-LABEL: all_true_8_i16:
 ; CHECK:         .functype all_true_8_i16 (v128) -> (i32)
 ; CHECK-NEXT:  # %bb.0:
-; CHECK-NEXT:    v128.const $push0=, 0, 0, 0, 0, 0, 0, 0, 0
-; CHECK-NEXT:    i16x8.eq $push1=, $0, $pop0
-; CHECK-NEXT:    v128.any_true $push2=, $pop1
-; CHECK-NEXT:    i32.const $push3=, -1
-; CHECK-NEXT:    i32.xor $push4=, $pop2, $pop3
-; CHECK-NEXT:    i32.const $push5=, 1
-; CHECK-NEXT:    i32.and $push6=, $pop4, $pop5
-; CHECK-NEXT:    return $pop6
+; CHECK-NEXT:    i16x8.all_true $push0=, $0
+; CHECK-NEXT:    return $pop0
   %1 = icmp eq <8 x i16> %v, zeroinitializer
   %2 = bitcast <8 x i1> %1 to i8
   %3 = icmp eq i8 %2, 0
@@ -67,14 +49,8 @@ define i32 @all_true_2_i64(<2 x i64> %v) {
 ; CHECK-LABEL: all_true_2_i64:
 ; CHECK:         .functype all_true_2_i64 (v128) -> (i32)
 ; CHECK-NEXT:  # %bb.0:
-; CHECK-NEXT:    v128.const $push0=, 0, 0
-; CHECK-NEXT:    i64x2.eq $push1=, $0, $pop0
-; CHECK-NEXT:    v128.any_true $push2=, $pop1
-; CHECK-NEXT:    i32.const $push3=, -1
-; CHECK-NEXT:    i32.xor $push4=, $pop2, $pop3
-; CHECK-NEXT:    i32.const $push5=, 1
-; CHECK-NEXT:    i32.and $push6=, $pop4, $pop5
-; CHECK-NEXT:    return $pop6
+; CHECK-NEXT:    i64x2.all_true $push0=, $0
+; CHECK-NEXT:    return $pop0
   %1 = icmp eq <2 x i64> %v, zeroinitializer
   %2 = bitcast <2 x i1> %1 to i2
   %3 = icmp eq i2 %2, 0

llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll

@@ -1086,9 +1086,9 @@ define i1 @test_cmp_v16i8(<16 x i8> %x) {
 ; CHECK-LABEL: test_cmp_v16i8:
 ; CHECK:         .functype test_cmp_v16i8 (v128) -> (i32)
 ; CHECK-NEXT:  # %bb.0:
-; CHECK-NEXT:    v128.const $push0=, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
-; CHECK-NEXT:    i8x16.eq $push1=, $0, $pop0
-; CHECK-NEXT:    v128.any_true $push2=, $pop1
+; CHECK-NEXT:    i8x16.all_true $push0=, $0
+; CHECK-NEXT:    i32.const $push1=, 1
+; CHECK-NEXT:    i32.xor $push2=, $pop0, $pop1
 ; CHECK-NEXT:    return $pop2
   %zero = icmp eq <16 x i8> %x, zeroinitializer
   %ret = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> %zero)