[M68k] implement -mxgot

Author: knickish

llvm/lib/Target/M68k/M68k.td

@@ -65,6 +65,9 @@ foreach i = {0-7} in
       SubtargetFeature<"reserve-d"#i, "UserReservedRegister[M68k::D"#i#"]",
                        "true", "Reserve D"#i#" register">;
 
+def FeatureXGOT
+    : SubtargetFeature<"xgot", "UseXGOT", "true", "Assume 32-bit GOT">;
+
 //===----------------------------------------------------------------------===//
 // M68k processors supported.
 //===----------------------------------------------------------------------===//

llvm/lib/Target/M68k/M68kInstrInfo.cpp

@@ -936,6 +936,7 @@ struct M68kGlobalBaseReg : public MachineFunctionPass {
   bool runOnMachineFunction(MachineFunction &MF) override {
     const M68kSubtarget &STI = MF.getSubtarget<M68kSubtarget>();
     M68kMachineFunctionInfo *MxFI = MF.getInfo<M68kMachineFunctionInfo>();
+    MachineRegisterInfo &RegInfo = MF.getRegInfo();
 
     unsigned GlobalBaseReg = MxFI->getGlobalBaseReg();
 
@@ -949,9 +950,29 @@ struct M68kGlobalBaseReg : public MachineFunctionPass {
     DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
     const M68kInstrInfo *TII = STI.getInstrInfo();
 
-    // Generate lea (__GLOBAL_OFFSET_TABLE_,%PC), %A5
-    BuildMI(FirstMBB, MBBI, DL, TII->get(M68k::LEA32q), GlobalBaseReg)
-        .addExternalSymbol("_GLOBAL_OFFSET_TABLE_", M68kII::MO_GOTPCREL);
+    if (STI.useXGOT()) {
+      // Generate the following, as PC relative addressing is limited to i16
+      // offset
+      //  lea (0,%PC), %A5
+      //  lea _GLOBAL_OFFSET_TABLE_, %AX
+      //  suba.l %AX, %A5
+      // where %AX can be any other assigned address register.
+      // This should allow programs in a >16bit PC state to still use GOTPCREL
+      // addressing.
+      Register LoadPC = RegInfo.createVirtualRegister(&M68k::AR32_NOSPRegClass);
+      Register LoadGOT =
+          RegInfo.createVirtualRegister(&M68k::AR32_NOSPRegClass);
+      BuildMI(FirstMBB, MBBI, DL, TII->get(M68k::LEA32q), LoadPC).addImm(0);
+      BuildMI(FirstMBB, MBBI, DL, TII->get(M68k::LEA32b), LoadGOT)
+          .addExternalSymbol("_GLOBAL_OFFSET_TABLE_");
+      BuildMI(FirstMBB, MBBI, DL, TII->get(M68k::SUB32ar), GlobalBaseReg)
+          .addReg(LoadGOT)
+          .addReg(LoadPC);
+    } else {
+      // Generate lea (__GLOBAL_OFFSET_TABLE_,%PC), %A5
+      BuildMI(FirstMBB, MBBI, DL, TII->get(M68k::LEA32q), GlobalBaseReg)
+          .addExternalSymbol("_GLOBAL_OFFSET_TABLE_", M68kII::MO_GOTPCREL);
+    }
 
     return true;
   }

llvm/lib/Target/M68k/M68kSubtarget.cpp

@@ -25,6 +25,7 @@
 #include "llvm/IR/Attributes.h"
 #include "llvm/IR/Function.h"
 #include "llvm/MC/TargetRegistry.h"
+#include "llvm/Support/CodeGen.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ErrorHandling.h"
 
@@ -50,7 +51,8 @@ void M68kSubtarget::anchor() {}
 
 M68kSubtarget::M68kSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
                              const M68kTargetMachine &TM)
-    : M68kGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), TM(TM), TSInfo(),
+    : M68kGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
+      UseXGOT(this->useXGOT()), TM(TM), TSInfo(),
       InstrInfo(initializeSubtargetDependencies(CPU, TT, FS, TM)),
       FrameLowering(*this, this->getStackAlignment()), TLInfo(TM, *this),
       TargetTriple(TT) {

llvm/lib/Target/M68k/M68kSubtarget.h

@@ -51,6 +51,8 @@ class M68kSubtarget : public M68kGenSubtargetInfo {
   enum SubtargetEnum { M00, M10, M20, M30, M40, M60 };
   SubtargetEnum SubtargetKind = M00;
 
+  bool UseXGOT = false;
+
   enum FPKindEnum { M881, M882 };
   std::optional<FPKindEnum> FPUKind;
 
@@ -98,6 +100,8 @@ class M68kSubtarget : public M68kGenSubtargetInfo {
 
   bool useSmallSection() const { return UseSmallSection; }
 
+  bool useXGOT() const { return UseXGOT; }
+
   const Triple &getTargetTriple() const { return TargetTriple; }
 
   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }

llvm/test/CodeGen/M68k/xgot.ll

@@ -0,0 +1,51 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -mtriple=m68k --show-mc-encoding -mattr=+xgot -relocation-model=pic -code-model=large < %s | FileCheck %s
+
+@VBRTag = external global [2147483647 x i8]
+
+define i1 @folded_offset(i32 %conv29) {
+; CHECK-LABEL: folded_offset:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  ; %bb.0: ; %entry
+; CHECK-NEXT:    lea (0,%pc), %a0 ; encoding: [0x41,0xfa,0x00,0x00]
+; CHECK-NEXT:    lea _GLOBAL_OFFSET_TABLE_, %a1 ; encoding: [0x43,0xf9,A,A,A,A]
+; CHECK-NEXT:    ; fixup A - offset: 2, value: _GLOBAL_OFFSET_TABLE_, kind: FK_Data_4
+; CHECK-NEXT:    suba.l %a0, %a1 ; encoding: [0x93,0xc8]
+; CHECK-NEXT:    move.l #VBRTag@GOTOFF, %d0 ; encoding: [0x20,0x3c,A,A,A,A]
+; CHECK-NEXT:    ; fixup A - offset: 2, value: VBRTag@GOTOFF, kind: FK_Data_4
+; CHECK-NEXT:    move.b (1,%a1,%d0), %d0 ; encoding: [0x10,0x31,0x08,0x01]
+; CHECK-NEXT:    ext.w %d0 ; encoding: [0x48,0x80]
+; CHECK-NEXT:    ext.l %d0 ; encoding: [0x48,0xc0]
+; CHECK-NEXT:    sub.l (4,%sp), %d0 ; encoding: [0x90,0xaf,0x00,0x04]
+; CHECK-NEXT:    seq %d0 ; encoding: [0x57,0xc0]
+; CHECK-NEXT:    rts ; encoding: [0x4e,0x75]
+entry:
+  %0 = load i8, ptr getelementptr inbounds ([2147483647 x i8], ptr @VBRTag, i32 0, i32 1), align 1
+  %conv30 = sext i8 %0 to i32
+  %cmp31.not = icmp eq i32 %conv30, %conv29
+  ret i1 %cmp31.not
+}
+
+define i1 @non_folded_offset(i32 %conv29) {
+; CHECK-LABEL: non_folded_offset:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  ; %bb.0: ; %entry
+; CHECK-NEXT:    lea (0,%pc), %a0 ; encoding: [0x41,0xfa,0x00,0x00]
+; CHECK-NEXT:    lea _GLOBAL_OFFSET_TABLE_, %a1 ; encoding: [0x43,0xf9,A,A,A,A]
+; CHECK-NEXT:    ; fixup A - offset: 2, value: _GLOBAL_OFFSET_TABLE_, kind: FK_Data_4
+; CHECK-NEXT:    suba.l %a0, %a1 ; encoding: [0x93,0xc8]
+; CHECK-NEXT:    move.l #2147483645, %d0 ; encoding: [0x20,0x3c,0x7f,0xff,0xff,0xfd]
+; CHECK-NEXT:    adda.l #VBRTag@GOTOFF, %a1 ; encoding: [0xd3,0xfc,A,A,A,A]
+; CHECK-NEXT:    ; fixup A - offset: 2, value: VBRTag@GOTOFF, kind: FK_Data_4
+; CHECK-NEXT:    move.b (0,%a1,%d0), %d0 ; encoding: [0x10,0x31,0x08,0x00]
+; CHECK-NEXT:    ext.w %d0 ; encoding: [0x48,0x80]
+; CHECK-NEXT:    ext.l %d0 ; encoding: [0x48,0xc0]
+; CHECK-NEXT:    sub.l (4,%sp), %d0 ; encoding: [0x90,0xaf,0x00,0x04]
+; CHECK-NEXT:    seq %d0 ; encoding: [0x57,0xc0]
+; CHECK-NEXT:    rts ; encoding: [0x4e,0x75]
+entry:
+  %0 = load i8, ptr getelementptr inbounds ([2147483647 x i8], ptr @VBRTag, i32 0, i32 2147483645), align 1
+  %conv30 = sext i8 %0 to i32
+  %cmp31.not = icmp eq i32 %conv30, %conv29
+  ret i1 %cmp31.not
+}