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sunshaocesunshaoce
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[RISCV][GlobalIsel] Reduce constant pool usage without FP extension (#158346)
The recognition range can be extended later.
1 parent 895cda7 commit 4452fbd

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6 files changed

+354
-301
lines changed

6 files changed

+354
-301
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp‎

Lines changed: 26 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -572,7 +572,9 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
572572
.legalFor(ST.hasStdExtF(), {s32})
573573
.legalFor(ST.hasStdExtD(), {s64})
574574
.legalFor(ST.hasStdExtZfh(), {s16})
575-
.lowerFor({s32, s64, s128});
575+
.customFor(!ST.is64Bit(), {s32})
576+
.customFor(ST.is64Bit(), {s32, s64})
577+
.lowerFor({s64, s128});
576578

577579
getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
578580
.legalFor(ST.hasStdExtF(), {{sXLen, s32}})
@@ -869,6 +871,17 @@ bool RISCVLegalizerInfo::shouldBeInConstantPool(const APInt &APImm,
869871
return !(!SeqLo.empty() && (SeqLo.size() + 2) <= STI.getMaxBuildIntsCost());
870872
}
871873

874+
bool RISCVLegalizerInfo::shouldBeInFConstantPool(const APFloat &APF) const {
875+
[[maybe_unused]] unsigned Size = APF.getSizeInBits(APF.getSemantics());
876+
assert((Size == 32 || Size == 64) && "Only support f32 and f64");
877+
878+
int64_t Imm = APF.bitcastToAPInt().getSExtValue();
879+
RISCVMatInt::InstSeq Seq = RISCVMatInt::generateInstSeq(Imm, STI);
880+
if (Seq.size() <= STI.getMaxBuildIntsCost())
881+
return false;
882+
return true;
883+
}
884+
872885
bool RISCVLegalizerInfo::legalizeVScale(MachineInstr &MI,
873886
MachineIRBuilder &MIB) const {
874887
const LLT XLenTy(STI.getXLenVT());
@@ -1358,7 +1371,18 @@ bool RISCVLegalizerInfo::legalizeCustom(
13581371
return false;
13591372
case TargetOpcode::G_ABS:
13601373
return Helper.lowerAbsToMaxNeg(MI);
1361-
// TODO: G_FCONSTANT
1374+
case TargetOpcode::G_FCONSTANT: {
1375+
const APFloat FVal = MI.getOperand(1).getFPImm()->getValueAPF();
1376+
if (shouldBeInFConstantPool(FVal))
1377+
return Helper.lowerFConstant(MI);
1378+
1379+
// Convert G_FCONSTANT to G_CONSTANT.
1380+
Register DstReg = MI.getOperand(0).getReg();
1381+
MIRBuilder.buildConstant(DstReg, FVal.bitcastToAPInt());
1382+
1383+
MI.eraseFromParent();
1384+
return true;
1385+
}
13621386
case TargetOpcode::G_CONSTANT: {
13631387
const Function &F = MF.getFunction();
13641388
// TODO: if PSI and BFI are present, add " ||

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,7 @@ class RISCVLegalizerInfo : public LegalizerInfo {
3939

4040
private:
4141
bool shouldBeInConstantPool(const APInt &APImm, bool ShouldOptForSize) const;
42+
bool shouldBeInFConstantPool(const APFloat &APImm) const;
4243
bool legalizeShlAshrLshr(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
4344
GISelChangeObserver &Observer) const;
4445

‎llvm/test/CodeGen/RISCV/GlobalISel/constantpool.ll‎

Lines changed: 116 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -15,47 +15,37 @@
1515
define void @constpool_f32(ptr %p) {
1616
; RV32-SMALL-LABEL: constpool_f32:
1717
; RV32-SMALL: # %bb.0:
18-
; RV32-SMALL-NEXT: lui a1, %hi(.LCPI0_0)
19-
; RV32-SMALL-NEXT: lw a1, %lo(.LCPI0_0)(a1)
18+
; RV32-SMALL-NEXT: lui a1, 260096
2019
; RV32-SMALL-NEXT: sw a1, 0(a0)
2120
; RV32-SMALL-NEXT: ret
2221
;
2322
; RV32-MEDIUM-LABEL: constpool_f32:
2423
; RV32-MEDIUM: # %bb.0:
25-
; RV32-MEDIUM-NEXT: .Lpcrel_hi0:
26-
; RV32-MEDIUM-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
27-
; RV32-MEDIUM-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi0)(a1)
24+
; RV32-MEDIUM-NEXT: lui a1, 260096
2825
; RV32-MEDIUM-NEXT: sw a1, 0(a0)
2926
; RV32-MEDIUM-NEXT: ret
3027
;
3128
; RV32-PIC-LABEL: constpool_f32:
3229
; RV32-PIC: # %bb.0:
33-
; RV32-PIC-NEXT: .Lpcrel_hi0:
34-
; RV32-PIC-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
35-
; RV32-PIC-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi0)(a1)
30+
; RV32-PIC-NEXT: lui a1, 260096
3631
; RV32-PIC-NEXT: sw a1, 0(a0)
3732
; RV32-PIC-NEXT: ret
3833
;
3934
; RV64-SMALL-LABEL: constpool_f32:
4035
; RV64-SMALL: # %bb.0:
41-
; RV64-SMALL-NEXT: lui a1, %hi(.LCPI0_0)
42-
; RV64-SMALL-NEXT: lw a1, %lo(.LCPI0_0)(a1)
36+
; RV64-SMALL-NEXT: lui a1, 260096
4337
; RV64-SMALL-NEXT: sw a1, 0(a0)
4438
; RV64-SMALL-NEXT: ret
4539
;
4640
; RV64-MEDIUM-LABEL: constpool_f32:
4741
; RV64-MEDIUM: # %bb.0:
48-
; RV64-MEDIUM-NEXT: .Lpcrel_hi0:
49-
; RV64-MEDIUM-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
50-
; RV64-MEDIUM-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi0)(a1)
42+
; RV64-MEDIUM-NEXT: lui a1, 260096
5143
; RV64-MEDIUM-NEXT: sw a1, 0(a0)
5244
; RV64-MEDIUM-NEXT: ret
5345
;
5446
; RV64-PIC-LABEL: constpool_f32:
5547
; RV64-PIC: # %bb.0:
56-
; RV64-PIC-NEXT: .Lpcrel_hi0:
57-
; RV64-PIC-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
58-
; RV64-PIC-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi0)(a1)
48+
; RV64-PIC-NEXT: lui a1, 260096
5949
; RV64-PIC-NEXT: sw a1, 0(a0)
6050
; RV64-PIC-NEXT: ret
6151
store float 1.0, ptr %p
@@ -75,9 +65,9 @@ define void @constpool_f64(ptr %p) {
7565
;
7666
; RV32-MEDIUM-LABEL: constpool_f64:
7767
; RV32-MEDIUM: # %bb.0:
78-
; RV32-MEDIUM-NEXT: .Lpcrel_hi1:
68+
; RV32-MEDIUM-NEXT: .Lpcrel_hi0:
7969
; RV32-MEDIUM-NEXT: auipc a1, %pcrel_hi(.LCPI1_0)
80-
; RV32-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.Lpcrel_hi1)
70+
; RV32-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.Lpcrel_hi0)
8171
; RV32-MEDIUM-NEXT: lw a2, 0(a1)
8272
; RV32-MEDIUM-NEXT: lw a1, 4(a1)
8373
; RV32-MEDIUM-NEXT: sw a2, 0(a0)
@@ -86,9 +76,9 @@ define void @constpool_f64(ptr %p) {
8676
;
8777
; RV32-PIC-LABEL: constpool_f64:
8878
; RV32-PIC: # %bb.0:
89-
; RV32-PIC-NEXT: .Lpcrel_hi1:
79+
; RV32-PIC-NEXT: .Lpcrel_hi0:
9080
; RV32-PIC-NEXT: auipc a1, %pcrel_hi(.LCPI1_0)
91-
; RV32-PIC-NEXT: addi a1, a1, %pcrel_lo(.Lpcrel_hi1)
81+
; RV32-PIC-NEXT: addi a1, a1, %pcrel_lo(.Lpcrel_hi0)
9282
; RV32-PIC-NEXT: lw a2, 0(a1)
9383
; RV32-PIC-NEXT: lw a1, 4(a1)
9484
; RV32-PIC-NEXT: sw a2, 0(a0)
@@ -97,26 +87,124 @@ define void @constpool_f64(ptr %p) {
9787
;
9888
; RV64-SMALL-LABEL: constpool_f64:
9989
; RV64-SMALL: # %bb.0:
100-
; RV64-SMALL-NEXT: lui a1, %hi(.LCPI1_0)
101-
; RV64-SMALL-NEXT: ld a1, %lo(.LCPI1_0)(a1)
90+
; RV64-SMALL-NEXT: li a1, 1023
91+
; RV64-SMALL-NEXT: slli a1, a1, 52
10292
; RV64-SMALL-NEXT: sd a1, 0(a0)
10393
; RV64-SMALL-NEXT: ret
10494
;
10595
; RV64-MEDIUM-LABEL: constpool_f64:
10696
; RV64-MEDIUM: # %bb.0:
107-
; RV64-MEDIUM-NEXT: .Lpcrel_hi1:
108-
; RV64-MEDIUM-NEXT: auipc a1, %pcrel_hi(.LCPI1_0)
109-
; RV64-MEDIUM-NEXT: ld a1, %pcrel_lo(.Lpcrel_hi1)(a1)
97+
; RV64-MEDIUM-NEXT: li a1, 1023
98+
; RV64-MEDIUM-NEXT: slli a1, a1, 52
11099
; RV64-MEDIUM-NEXT: sd a1, 0(a0)
111100
; RV64-MEDIUM-NEXT: ret
112101
;
113102
; RV64-PIC-LABEL: constpool_f64:
114103
; RV64-PIC: # %bb.0:
115-
; RV64-PIC-NEXT: .Lpcrel_hi1:
116-
; RV64-PIC-NEXT: auipc a1, %pcrel_hi(.LCPI1_0)
117-
; RV64-PIC-NEXT: ld a1, %pcrel_lo(.Lpcrel_hi1)(a1)
104+
; RV64-PIC-NEXT: li a1, 1023
105+
; RV64-PIC-NEXT: slli a1, a1, 52
118106
; RV64-PIC-NEXT: sd a1, 0(a0)
119107
; RV64-PIC-NEXT: ret
120108
store double 1.0, ptr %p
121109
ret void
122110
}
111+
112+
define void @constpool_f32_1234_5(ptr %p) {
113+
; RV32-SMALL-LABEL: constpool_f32_1234_5:
114+
; RV32-SMALL: # %bb.0:
115+
; RV32-SMALL-NEXT: lui a1, 280997
116+
; RV32-SMALL-NEXT: sw a1, 0(a0)
117+
; RV32-SMALL-NEXT: ret
118+
;
119+
; RV32-MEDIUM-LABEL: constpool_f32_1234_5:
120+
; RV32-MEDIUM: # %bb.0:
121+
; RV32-MEDIUM-NEXT: lui a1, 280997
122+
; RV32-MEDIUM-NEXT: sw a1, 0(a0)
123+
; RV32-MEDIUM-NEXT: ret
124+
;
125+
; RV32-PIC-LABEL: constpool_f32_1234_5:
126+
; RV32-PIC: # %bb.0:
127+
; RV32-PIC-NEXT: lui a1, 280997
128+
; RV32-PIC-NEXT: sw a1, 0(a0)
129+
; RV32-PIC-NEXT: ret
130+
;
131+
; RV64-SMALL-LABEL: constpool_f32_1234_5:
132+
; RV64-SMALL: # %bb.0:
133+
; RV64-SMALL-NEXT: lui a1, 280997
134+
; RV64-SMALL-NEXT: sw a1, 0(a0)
135+
; RV64-SMALL-NEXT: ret
136+
;
137+
; RV64-MEDIUM-LABEL: constpool_f32_1234_5:
138+
; RV64-MEDIUM: # %bb.0:
139+
; RV64-MEDIUM-NEXT: lui a1, 280997
140+
; RV64-MEDIUM-NEXT: sw a1, 0(a0)
141+
; RV64-MEDIUM-NEXT: ret
142+
;
143+
; RV64-PIC-LABEL: constpool_f32_1234_5:
144+
; RV64-PIC: # %bb.0:
145+
; RV64-PIC-NEXT: lui a1, 280997
146+
; RV64-PIC-NEXT: sw a1, 0(a0)
147+
; RV64-PIC-NEXT: ret
148+
store float 1.234500e+03, ptr %p
149+
ret void
150+
}
151+
152+
define void @constpool_f64_1234_5(ptr %p) {
153+
; RV32-SMALL-LABEL: constpool_f64_1234_5:
154+
; RV32-SMALL: # %bb.0:
155+
; RV32-SMALL-NEXT: lui a1, %hi(.LCPI3_0)
156+
; RV32-SMALL-NEXT: addi a1, a1, %lo(.LCPI3_0)
157+
; RV32-SMALL-NEXT: lw a2, 0(a1)
158+
; RV32-SMALL-NEXT: lw a1, 4(a1)
159+
; RV32-SMALL-NEXT: sw a2, 0(a0)
160+
; RV32-SMALL-NEXT: sw a1, 4(a0)
161+
; RV32-SMALL-NEXT: ret
162+
;
163+
; RV32-MEDIUM-LABEL: constpool_f64_1234_5:
164+
; RV32-MEDIUM: # %bb.0:
165+
; RV32-MEDIUM-NEXT: .Lpcrel_hi1:
166+
; RV32-MEDIUM-NEXT: auipc a1, %pcrel_hi(.LCPI3_0)
167+
; RV32-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.Lpcrel_hi1)
168+
; RV32-MEDIUM-NEXT: lw a2, 0(a1)
169+
; RV32-MEDIUM-NEXT: lw a1, 4(a1)
170+
; RV32-MEDIUM-NEXT: sw a2, 0(a0)
171+
; RV32-MEDIUM-NEXT: sw a1, 4(a0)
172+
; RV32-MEDIUM-NEXT: ret
173+
;
174+
; RV32-PIC-LABEL: constpool_f64_1234_5:
175+
; RV32-PIC: # %bb.0:
176+
; RV32-PIC-NEXT: .Lpcrel_hi1:
177+
; RV32-PIC-NEXT: auipc a1, %pcrel_hi(.LCPI3_0)
178+
; RV32-PIC-NEXT: addi a1, a1, %pcrel_lo(.Lpcrel_hi1)
179+
; RV32-PIC-NEXT: lw a2, 0(a1)
180+
; RV32-PIC-NEXT: lw a1, 4(a1)
181+
; RV32-PIC-NEXT: sw a2, 0(a0)
182+
; RV32-PIC-NEXT: sw a1, 4(a0)
183+
; RV32-PIC-NEXT: ret
184+
;
185+
; RV64-SMALL-LABEL: constpool_f64_1234_5:
186+
; RV64-SMALL: # %bb.0:
187+
; RV64-SMALL-NEXT: lui a1, 517
188+
; RV64-SMALL-NEXT: addi a1, a1, -1627
189+
; RV64-SMALL-NEXT: slli a1, a1, 41
190+
; RV64-SMALL-NEXT: sd a1, 0(a0)
191+
; RV64-SMALL-NEXT: ret
192+
;
193+
; RV64-MEDIUM-LABEL: constpool_f64_1234_5:
194+
; RV64-MEDIUM: # %bb.0:
195+
; RV64-MEDIUM-NEXT: lui a1, 517
196+
; RV64-MEDIUM-NEXT: addi a1, a1, -1627
197+
; RV64-MEDIUM-NEXT: slli a1, a1, 41
198+
; RV64-MEDIUM-NEXT: sd a1, 0(a0)
199+
; RV64-MEDIUM-NEXT: ret
200+
;
201+
; RV64-PIC-LABEL: constpool_f64_1234_5:
202+
; RV64-PIC: # %bb.0:
203+
; RV64-PIC-NEXT: lui a1, 517
204+
; RV64-PIC-NEXT: addi a1, a1, -1627
205+
; RV64-PIC-NEXT: slli a1, a1, 41
206+
; RV64-PIC-NEXT: sd a1, 0(a0)
207+
; RV64-PIC-NEXT: ret
208+
store double 1.234500e+03, ptr %p
209+
ret void
210+
}

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