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‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -14,12 +14,12 @@
1414
// Operand and SDNode transformation definitions.
1515
//===----------------------------------------------------------------------===//
1616

17-
def SDT_StoreMultiple : SDTypeProfile<0, 4, [SDTCisSameAs<0, 1>,
18-
SDTCisSameAs<1, 3>,
19-
SDTCisPtrTy<2>,
20-
SDTCisVT<3, XLenVT>]>;
17+
def SDT_SetMultiple : SDTypeProfile<0, 4, [SDTCisSameAs<0, 1>,
18+
SDTCisSameAs<1, 3>,
19+
SDTCisPtrTy<2>,
20+
SDTCisVT<3, XLenVT>]>;
2121

22-
def qc_setwmi : RVSDNode<"QC_SETWMI", SDT_StoreMultiple,
22+
def qc_setwmi : RVSDNode<"QC_SETWMI", SDT_SetMultiple,
2323
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
2424

2525
def uimm5nonzero : RISCVOp<XLenVT>,

‎llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.cpp‎

Lines changed: 30 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -69,8 +69,7 @@ SDValue RISCVSelectionDAGInfo::EmitTargetCodeForMemset(
6969
SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
7070
SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline,
7171
MachinePointerInfo DstPtrInfo) const {
72-
const RISCVSubtarget &Subtarget =
73-
DAG.getMachineFunction().getSubtarget<RISCVSubtarget>();
72+
const auto &Subtarget = DAG.getSubtarget<RISCVSubtarget>();
7473
// We currently do this only for Xqcilsm
7574
if (!Subtarget.hasVendorXqcilsm())
7675
return SDValue();
@@ -83,7 +82,7 @@ SDValue RISCVSelectionDAGInfo::EmitTargetCodeForMemset(
8382
uint64_t NumberOfBytesToWrite = ConstantSize->getZExtValue();
8483

8584
// Do this only if it is word aligned and we write multiple of 4 bytes.
86-
if (!((Alignment.value() & 3) == 0 && (NumberOfBytesToWrite & 3) == 0))
85+
if (!(Alignment.value() >= 4) || !((NumberOfBytesToWrite & 3) == 0))
8786
return SDValue();
8887

8988
SmallVector<SDValue, 8> OutChains;
@@ -104,7 +103,7 @@ SDValue RISCVSelectionDAGInfo::EmitTargetCodeForMemset(
104103
if ((Src.getValueType() == MVT::i8) && !IsZeroVal)
105104
// Replicate byte to word by multiplication with 0x01010101.
106105
SrcValueReplicated = DAG.getNode(ISD::MUL, dl, MVT::i32, SrcValueReplicated,
107-
DAG.getConstant(16843009, dl, MVT::i32));
106+
DAG.getConstant(0x01010101ul, dl, MVT::i32));
108107

109108
// We limit a QC_SETWMI to 16 words or less to improve interruptibility.
110109
// So for 1-16 words we use a single QC_SETWMI:
@@ -128,38 +127,38 @@ SDValue RISCVSelectionDAGInfo::EmitTargetCodeForMemset(
128127
// QC_SETWMI R2, R0, N, 124
129128
//
130129
// For 48 words or more, call the target independent memset
130+
if ( NumberOfWords >= 48)
131+
return SDValue();
132+
131133
if (NumberOfWords <= 16) {
132134
// 1 - 16 words
133135
SizeWords = DAG.getTargetConstant(NumberOfWords, dl, MVT::i32);
134136
SDValue OffsetSetwmi = DAG.getTargetConstant(0, dl, MVT::i32);
135137
return getSetwmiNode(SizeWords, OffsetSetwmi);
136-
} else if (NumberOfWords <= 47) {
137-
if (NumberOfWords <= 32) {
138-
// 17 - 32 words
139-
SizeWords = DAG.getTargetConstant(NumberOfWords - 16, dl, MVT::i32);
140-
OffsetSetwmi = DAG.getTargetConstant(64, dl, MVT::i32);
141-
OutChains.push_back(getSetwmiNode(SizeWords, OffsetSetwmi));
142-
143-
SizeWords = DAG.getTargetConstant(16, dl, MVT::i32);
144-
OffsetSetwmi = DAG.getTargetConstant(0, dl, MVT::i32);
145-
OutChains.push_back(getSetwmiNode(SizeWords, OffsetSetwmi));
146-
} else {
147-
// 33 - 47 words
148-
SizeWords = DAG.getTargetConstant(NumberOfWords - 31, dl, MVT::i32);
149-
OffsetSetwmi = DAG.getTargetConstant(124, dl, MVT::i32);
150-
OutChains.push_back(getSetwmiNode(SizeWords, OffsetSetwmi));
151-
152-
SizeWords = DAG.getTargetConstant(15, dl, MVT::i32);
153-
OffsetSetwmi = DAG.getTargetConstant(64, dl, MVT::i32);
154-
OutChains.push_back(getSetwmiNode(SizeWords, OffsetSetwmi));
155-
156-
SizeWords = DAG.getTargetConstant(16, dl, MVT::i32);
157-
OffsetSetwmi = DAG.getTargetConstant(0, dl, MVT::i32);
158-
OutChains.push_back(getSetwmiNode(SizeWords, OffsetSetwmi));
159-
}
160-
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
161138
}
162139

163-
// >= 48 words. Call target independent memset.
164-
return SDValue();
140+
if (NumberOfWords <= 32) {
141+
// 17 - 32 words
142+
SizeWords = DAG.getTargetConstant(NumberOfWords - 16, dl, MVT::i32);
143+
OffsetSetwmi = DAG.getTargetConstant(64, dl, MVT::i32);
144+
OutChains.push_back(getSetwmiNode(SizeWords, OffsetSetwmi));
145+
146+
SizeWords = DAG.getTargetConstant(16, dl, MVT::i32);
147+
OffsetSetwmi = DAG.getTargetConstant(0, dl, MVT::i32);
148+
OutChains.push_back(getSetwmiNode(SizeWords, OffsetSetwmi));
149+
} else {
150+
// 33 - 47 words
151+
SizeWords = DAG.getTargetConstant(NumberOfWords - 31, dl, MVT::i32);
152+
OffsetSetwmi = DAG.getTargetConstant(124, dl, MVT::i32);
153+
OutChains.push_back(getSetwmiNode(SizeWords, OffsetSetwmi));
154+
155+
SizeWords = DAG.getTargetConstant(15, dl, MVT::i32);
156+
OffsetSetwmi = DAG.getTargetConstant(64, dl, MVT::i32);
157+
OutChains.push_back(getSetwmiNode(SizeWords, OffsetSetwmi));
158+
159+
SizeWords = DAG.getTargetConstant(16, dl, MVT::i32);
160+
OffsetSetwmi = DAG.getTargetConstant(0, dl, MVT::i32);
161+
OutChains.push_back(getSetwmiNode(SizeWords, OffsetSetwmi));
162+
}
163+
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
165164
}

‎llvm/test/CodeGen/RISCV/xqcilsm-memset.ll‎

Lines changed: 0 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -299,30 +299,6 @@ entry:
299299
ret i32 %0
300300
}
301301

302-
define i32 @test6a() nounwind {
303-
; RV32I-LABEL: test6a:
304-
; RV32I: # %bb.0:
305-
; RV32I-NEXT: addi sp, sp, -16
306-
; RV32I-NEXT: sw zero, 12(sp)
307-
; RV32I-NEXT: lw a0, 12(sp)
308-
; RV32I-NEXT: addi sp, sp, 16
309-
; RV32I-NEXT: ret
310-
;
311-
; RV32IXQCILSM-LABEL: test6a:
312-
; RV32IXQCILSM: # %bb.0:
313-
; RV32IXQCILSM-NEXT: addi sp, sp, -16
314-
; RV32IXQCILSM-NEXT: sw zero, 12(sp)
315-
; RV32IXQCILSM-NEXT: lw a0, 12(sp)
316-
; RV32IXQCILSM-NEXT: addi sp, sp, 16
317-
; RV32IXQCILSM-NEXT: ret
318-
%x = alloca i32, align 4
319-
call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %x)
320-
store i32 0, ptr %x, align 4
321-
%x.0.x.0. = load volatile i32, ptr %x, align 4
322-
call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %x)
323-
ret i32 %x.0.x.0.
324-
}
325-
326302
define zeroext i8 @test6b_c() nounwind {
327303
; RV32I-LABEL: test6b_c:
328304
; RV32I: # %bb.0:
@@ -388,7 +364,6 @@ define i32 @test6b_l() nounwind {
388364
; RV32IXQCILSM-NEXT: lw a0, 12(sp)
389365
; RV32IXQCILSM-NEXT: addi sp, sp, 16
390366
; RV32IXQCILSM-NEXT: ret
391-
; RV32IXQCISLS-LABEL: test6b_l:
392367
entry:
393368
%x = alloca i32, align 4
394369
call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %x)

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