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[InstCombine] Infer nneg flag from shift users (#71947)
This patch sets `nneg` flag when the zext is only used by a shift. Alive2: https://alive2.llvm.org/ce/z/h3xKjP Compile-time impact: https://llvm-compile-time-tracker.com/compare.php?from=bd611264993f64decbce178d460caf1d1cb05f59&to=26bc473b239010bb24ff1bc39d58b42ecbbc4730&stat=instructions:u This is an alternative to #71906.
1 parent 01893b5 commit 44cdbef

17 files changed

+67
-58
lines changed

‎llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp‎

Lines changed: 12 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1221,9 +1221,18 @@ Instruction *InstCombinerImpl::visitZExt(ZExtInst &Zext) {
12211221
}
12221222
}
12231223

1224-
if (!Zext.hasNonNeg() && isKnownNonNegative(Src, DL, 0, &AC, &Zext, &DT)) {
1225-
Zext.setNonNeg();
1226-
return &Zext;
1224+
if (!Zext.hasNonNeg()) {
1225+
// If this zero extend is only used by a shift, add nneg flag.
1226+
if (Zext.hasOneUse() && SrcTy->getScalarSizeInBits() > 2 &&
1227+
match(Zext.user_back(), m_Shift(m_Value(), m_Specific(&Zext)))) {
1228+
Zext.setNonNeg();
1229+
return &Zext;
1230+
}
1231+
1232+
if (isKnownNonNegative(Src, DL, 0, &AC, &Zext, &DT)) {
1233+
Zext.setNonNeg();
1234+
return &Zext;
1235+
}
12271236
}
12281237

12291238
return nullptr;

‎llvm/test/Transforms/InstCombine/div-shift.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@ define <2 x i32> @t1vec(<2 x i16> %x, <2 x i32> %y) {
3838
; rdar://11721329
3939
define i64 @t2(i64 %x, i32 %y) {
4040
; CHECK-LABEL: @t2(
41-
; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[Y:%.*]] to i64
41+
; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i32 [[Y:%.*]] to i64
4242
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[X:%.*]], [[TMP1]]
4343
; CHECK-NEXT: ret i64 [[TMP2]]
4444
;
@@ -52,7 +52,7 @@ define i64 @t2(i64 %x, i32 %y) {
5252
define i64 @t3(i64 %x, i32 %y) {
5353
; CHECK-LABEL: @t3(
5454
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[Y:%.*]], 2
55-
; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
55+
; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[TMP1]] to i64
5656
; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[X:%.*]], [[TMP2]]
5757
; CHECK-NEXT: ret i64 [[TMP3]]
5858
;

‎llvm/test/Transforms/InstCombine/load-cmp.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -122,7 +122,7 @@ define i1 @test4(i32 %X) {
122122

123123
define i1 @test4_i16(i16 %X) {
124124
; CHECK-LABEL: @test4_i16(
125-
; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[X:%.*]] to i32
125+
; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i16 [[X:%.*]] to i32
126126
; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 933, [[TMP1]]
127127
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], 1
128128
; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[TMP3]], 0

‎llvm/test/Transforms/InstCombine/rem.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -249,7 +249,7 @@ define i32 @test4(i32 %X, i1 %C) {
249249

250250
define i32 @test5(i32 %X, i8 %B) {
251251
; CHECK-LABEL: @test5(
252-
; CHECK-NEXT: [[SHIFT_UPGRD_1:%.*]] = zext i8 [[B:%.*]] to i32
252+
; CHECK-NEXT: [[SHIFT_UPGRD_1:%.*]] = zext nneg i8 [[B:%.*]] to i32
253253
; CHECK-NEXT: [[AMT:%.*]] = shl nuw i32 32, [[SHIFT_UPGRD_1]]
254254
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[AMT]], -1
255255
; CHECK-NEXT: [[V:%.*]] = and i32 [[TMP1]], [[X:%.*]]

‎llvm/test/Transforms/InstCombine/select-bitext-bitwise-ops.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -73,7 +73,7 @@ define i64 @sel_false_val_is_a_masked_ashr_of_true_val1(i32 %x, i64 %y) {
7373
; CHECK-LABEL: @sel_false_val_is_a_masked_ashr_of_true_val1(
7474
; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2
7575
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897
76-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
76+
; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64
7777
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
7878
; CHECK-NEXT: ret i64 [[TMP4]]
7979
;
@@ -90,7 +90,7 @@ define i64 @sel_false_val_is_a_masked_ashr_of_true_val2(i32 %x, i64 %y) {
9090
; CHECK-LABEL: @sel_false_val_is_a_masked_ashr_of_true_val2(
9191
; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2
9292
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897
93-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
93+
; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64
9494
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
9595
; CHECK-NEXT: ret i64 [[TMP4]]
9696
;

‎llvm/test/Transforms/InstCombine/select-obo-peo-ops.ll‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -73,7 +73,7 @@ define i64 @test_shl_nuw_nsw__nuw_is_safe(i32 %x, i64 %y) {
7373
; CHECK-LABEL: @test_shl_nuw_nsw__nuw_is_safe(
7474
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
7575
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8
76-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
76+
; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64
7777
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
7878
; CHECK-NEXT: ret i64 [[TMP4]]
7979
;
@@ -90,7 +90,7 @@ define i64 @test_shl_nuw__nuw_is_safe(i32 %x, i64 %y) {
9090
; CHECK-LABEL: @test_shl_nuw__nuw_is_safe(
9191
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
9292
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8
93-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
93+
; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64
9494
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
9595
; CHECK-NEXT: ret i64 [[TMP4]]
9696
;
@@ -107,7 +107,7 @@ define i64 @test_shl_nsw__nuw_is_safe(i32 %x, i64 %y) {
107107
; CHECK-LABEL: @test_shl_nsw__nuw_is_safe(
108108
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
109109
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8
110-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
110+
; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64
111111
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
112112
; CHECK-NEXT: ret i64 [[TMP4]]
113113
;
@@ -124,7 +124,7 @@ define i64 @test_shl__nuw_is_safe(i32 %x, i64 %y) {
124124
; CHECK-LABEL: @test_shl__nuw_is_safe(
125125
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
126126
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8
127-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
127+
; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64
128128
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
129129
; CHECK-NEXT: ret i64 [[TMP4]]
130130
;
@@ -202,7 +202,7 @@ define i64 @test_shl_nuw_nsw__none_are_safe(i32 %x, i64 %y) {
202202
; CHECK-LABEL: @test_shl_nuw_nsw__none_are_safe(
203203
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
204204
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8
205-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
205+
; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64
206206
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
207207
; CHECK-NEXT: ret i64 [[TMP4]]
208208
;
@@ -219,7 +219,7 @@ define i64 @test_shl_nuw__none_are_safe(i32 %x, i64 %y) {
219219
; CHECK-LABEL: @test_shl_nuw__none_are_safe(
220220
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
221221
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8
222-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
222+
; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64
223223
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
224224
; CHECK-NEXT: ret i64 [[TMP4]]
225225
;
@@ -236,7 +236,7 @@ define i64 @test_shl_nsw__none_are_safe(i32 %x, i64 %y) {
236236
; CHECK-LABEL: @test_shl_nsw__none_are_safe(
237237
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
238238
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8
239-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
239+
; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64
240240
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
241241
; CHECK-NEXT: ret i64 [[TMP4]]
242242
;
@@ -253,7 +253,7 @@ define i64 @test_shl__none_are_safe(i32 %x, i64 %y) {
253253
; CHECK-LABEL: @test_shl__none_are_safe(
254254
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
255255
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8
256-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
256+
; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64
257257
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
258258
; CHECK-NEXT: ret i64 [[TMP4]]
259259
;
@@ -338,7 +338,7 @@ define i64 @test_ashr_exact__exact_is_safe(i32 %x, i64 %y) {
338338
; CHECK-LABEL: @test_ashr_exact__exact_is_safe(
339339
; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2
340340
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897
341-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
341+
; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64
342342
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
343343
; CHECK-NEXT: ret i64 [[TMP4]]
344344
;
@@ -355,7 +355,7 @@ define i64 @test_ashr__exact_is_safe(i32 %x, i64 %y) {
355355
; CHECK-LABEL: @test_ashr__exact_is_safe(
356356
; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2
357357
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897
358-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
358+
; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64
359359
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
360360
; CHECK-NEXT: ret i64 [[TMP4]]
361361
;
@@ -372,7 +372,7 @@ define i64 @test_ashr_exact__exact_is_unsafe(i32 %x, i64 %y) {
372372
; CHECK-LABEL: @test_ashr_exact__exact_is_unsafe(
373373
; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2
374374
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897
375-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
375+
; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64
376376
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
377377
; CHECK-NEXT: ret i64 [[TMP4]]
378378
;
@@ -389,7 +389,7 @@ define i64 @test_ashr__exact_is_unsafe(i32 %x, i64 %y) {
389389
; CHECK-LABEL: @test_ashr__exact_is_unsafe(
390390
; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2
391391
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897
392-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
392+
; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64
393393
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
394394
; CHECK-NEXT: ret i64 [[TMP4]]
395395
;

‎llvm/test/Transforms/InstCombine/shift-add-inseltpoison.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55

66
define i32 @shl_C1_add_A_C2_i32(i16 %A) {
77
; CHECK-LABEL: @shl_C1_add_A_C2_i32(
8-
; CHECK-NEXT: [[B:%.*]] = zext i16 [[A:%.*]] to i32
8+
; CHECK-NEXT: [[B:%.*]] = zext nneg i16 [[A:%.*]] to i32
99
; CHECK-NEXT: [[D:%.*]] = shl i32 192, [[B]]
1010
; CHECK-NEXT: ret i32 [[D]]
1111
;
@@ -39,7 +39,7 @@ define i32 @lshr_C1_add_A_C2_i32(i32 %A) {
3939

4040
define <4 x i32> @shl_C1_add_A_C2_v4i32(<4 x i16> %A) {
4141
; CHECK-LABEL: @shl_C1_add_A_C2_v4i32(
42-
; CHECK-NEXT: [[B:%.*]] = zext <4 x i16> [[A:%.*]] to <4 x i32>
42+
; CHECK-NEXT: [[B:%.*]] = zext nneg <4 x i16> [[A:%.*]] to <4 x i32>
4343
; CHECK-NEXT: [[D:%.*]] = shl <4 x i32> <i32 6, i32 4, i32 poison, i32 -458752>, [[B]]
4444
; CHECK-NEXT: ret <4 x i32> [[D]]
4545
;

‎llvm/test/Transforms/InstCombine/shift-add.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ declare void @use(i8)
77

88
define i32 @shl_C1_add_A_C2_i32(i16 %A) {
99
; CHECK-LABEL: @shl_C1_add_A_C2_i32(
10-
; CHECK-NEXT: [[B:%.*]] = zext i16 [[A:%.*]] to i32
10+
; CHECK-NEXT: [[B:%.*]] = zext nneg i16 [[A:%.*]] to i32
1111
; CHECK-NEXT: [[D:%.*]] = shl i32 192, [[B]]
1212
; CHECK-NEXT: ret i32 [[D]]
1313
;
@@ -41,7 +41,7 @@ define i32 @lshr_C1_add_A_C2_i32(i32 %A) {
4141

4242
define <4 x i32> @shl_C1_add_A_C2_v4i32(<4 x i16> %A) {
4343
; CHECK-LABEL: @shl_C1_add_A_C2_v4i32(
44-
; CHECK-NEXT: [[B:%.*]] = zext <4 x i16> [[A:%.*]] to <4 x i32>
44+
; CHECK-NEXT: [[B:%.*]] = zext nneg <4 x i16> [[A:%.*]] to <4 x i32>
4545
; CHECK-NEXT: [[D:%.*]] = shl <4 x i32> <i32 6, i32 4, i32 poison, i32 -458752>, [[B]]
4646
; CHECK-NEXT: ret <4 x i32> [[D]]
4747
;

‎llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-lshr.ll‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ define i1 @n0(i32 %x, i64 %y, i32 %len) {
1919
; CHECK-NEXT: [[T0:%.*]] = sub i32 32, [[LEN:%.*]]
2020
; CHECK-NEXT: [[T1:%.*]] = shl i32 [[X:%.*]], [[T0]]
2121
; CHECK-NEXT: [[T2:%.*]] = add i32 [[LEN]], -16
22-
; CHECK-NEXT: [[T2_WIDE:%.*]] = zext i32 [[T2]] to i64
22+
; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg i32 [[T2]] to i64
2323
; CHECK-NEXT: [[T3:%.*]] = lshr i64 [[Y:%.*]], [[T2_WIDE]]
2424
; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc i64 [[T3]] to i32
2525
; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[T3_TRUNC]]
@@ -79,7 +79,7 @@ define i1 @n2(i64 %y, i32 %len) {
7979
; CHECK-NEXT: [[T0:%.*]] = sub i32 32, [[LEN:%.*]]
8080
; CHECK-NEXT: [[T1:%.*]] = shl i32 131071, [[T0]]
8181
; CHECK-NEXT: [[T2:%.*]] = add i32 [[LEN]], -16
82-
; CHECK-NEXT: [[T2_WIDE:%.*]] = zext i32 [[T2]] to i64
82+
; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg i32 [[T2]] to i64
8383
; CHECK-NEXT: [[T3:%.*]] = lshr i64 [[Y:%.*]], [[T2_WIDE]]
8484
; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc i64 [[T3]] to i32
8585
; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[T3_TRUNC]]
@@ -137,7 +137,7 @@ define i1 @n4(i32 %x, i32 %len) {
137137
; CHECK-NEXT: [[T0:%.*]] = sub i32 32, [[LEN:%.*]]
138138
; CHECK-NEXT: [[T1:%.*]] = shl i32 [[X:%.*]], [[T0]]
139139
; CHECK-NEXT: [[T2:%.*]] = add i32 [[LEN]], -16
140-
; CHECK-NEXT: [[T2_WIDE:%.*]] = zext i32 [[T2]] to i64
140+
; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg i32 [[T2]] to i64
141141
; CHECK-NEXT: [[T3:%.*]] = lshr i64 262143, [[T2_WIDE]]
142142
; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc i64 [[T3]] to i32
143143
; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[T3_TRUNC]]
@@ -186,7 +186,7 @@ define <2 x i1> @n6_vec(<2 x i64> %y, <2 x i32> %len) {
186186
; CHECK-NEXT: [[T0:%.*]] = sub <2 x i32> <i32 32, i32 32>, [[LEN:%.*]]
187187
; CHECK-NEXT: [[T1:%.*]] = shl <2 x i32> <i32 65535, i32 131071>, [[T0]]
188188
; CHECK-NEXT: [[T2:%.*]] = add <2 x i32> [[LEN]], <i32 -16, i32 -16>
189-
; CHECK-NEXT: [[T2_WIDE:%.*]] = zext <2 x i32> [[T2]] to <2 x i64>
189+
; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg <2 x i32> [[T2]] to <2 x i64>
190190
; CHECK-NEXT: [[T3:%.*]] = lshr <2 x i64> [[Y:%.*]], [[T2_WIDE]]
191191
; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc <2 x i64> [[T3]] to <2 x i32>
192192
; CHECK-NEXT: [[T4:%.*]] = and <2 x i32> [[T1]], [[T3_TRUNC]]
@@ -227,7 +227,7 @@ define <2 x i1> @n8_vec(<2 x i32> %x, <2 x i32> %len) {
227227
; CHECK-NEXT: [[T0:%.*]] = sub <2 x i32> <i32 32, i32 32>, [[LEN:%.*]]
228228
; CHECK-NEXT: [[T1:%.*]] = shl <2 x i32> [[X:%.*]], [[T0]]
229229
; CHECK-NEXT: [[T2:%.*]] = add <2 x i32> [[LEN]], <i32 -16, i32 -16>
230-
; CHECK-NEXT: [[T2_WIDE:%.*]] = zext <2 x i32> [[T2]] to <2 x i64>
230+
; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg <2 x i32> [[T2]] to <2 x i64>
231231
; CHECK-NEXT: [[T3:%.*]] = lshr <2 x i64> <i64 131071, i64 262143>, [[T2_WIDE]]
232232
; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc <2 x i64> [[T3]] to <2 x i32>
233233
; CHECK-NEXT: [[T4:%.*]] = and <2 x i32> [[T1]], [[T3_TRUNC]]
@@ -272,7 +272,7 @@ define i1 @t10_almost_highest_bit(i32 %x, i64 %y, i32 %len) {
272272
; CHECK-NEXT: [[T0:%.*]] = sub i32 64, [[LEN:%.*]]
273273
; CHECK-NEXT: [[T1:%.*]] = shl i32 [[X:%.*]], [[T0]]
274274
; CHECK-NEXT: [[T2:%.*]] = add i32 [[LEN]], -2
275-
; CHECK-NEXT: [[T2_WIDE:%.*]] = zext i32 [[T2]] to i64
275+
; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg i32 [[T2]] to i64
276276
; CHECK-NEXT: [[T3:%.*]] = lshr i64 [[Y:%.*]], [[T2_WIDE]]
277277
; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc i64 [[T3]] to i32
278278
; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[T3_TRUNC]]
@@ -314,7 +314,7 @@ define i1 @t10_shift_by_one(i32 %x, i64 %y, i32 %len) {
314314
; CHECK-NEXT: [[T0:%.*]] = sub i32 64, [[LEN:%.*]]
315315
; CHECK-NEXT: [[T1:%.*]] = shl i32 [[X:%.*]], [[T0]]
316316
; CHECK-NEXT: [[T2:%.*]] = add i32 [[LEN]], -63
317-
; CHECK-NEXT: [[T2_WIDE:%.*]] = zext i32 [[T2]] to i64
317+
; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg i32 [[T2]] to i64
318318
; CHECK-NEXT: [[T3:%.*]] = lshr i64 [[Y:%.*]], [[T2_WIDE]]
319319
; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc i64 [[T3]] to i32
320320
; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[T3_TRUNC]]
@@ -338,7 +338,7 @@ define <2 x i1> @t11_zero_and_almost_bitwidth(<2 x i32> %x, <2 x i64> %y, <2 x i
338338
; CHECK-NEXT: [[T0:%.*]] = sub <2 x i32> <i32 64, i32 64>, [[LEN:%.*]]
339339
; CHECK-NEXT: [[T1:%.*]] = shl <2 x i32> [[X:%.*]], [[T0]]
340340
; CHECK-NEXT: [[T2:%.*]] = add <2 x i32> [[LEN]], <i32 -1, i32 -64>
341-
; CHECK-NEXT: [[T2_WIDE:%.*]] = zext <2 x i32> [[T2]] to <2 x i64>
341+
; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg <2 x i32> [[T2]] to <2 x i64>
342342
; CHECK-NEXT: [[T3:%.*]] = lshr <2 x i64> [[Y:%.*]], [[T2_WIDE]]
343343
; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc <2 x i64> [[T3]] to <2 x i32>
344344
; CHECK-NEXT: [[T4:%.*]] = and <2 x i32> [[T1]], [[T3_TRUNC]]
@@ -360,7 +360,7 @@ define <2 x i1> @n12_bad(<2 x i32> %x, <2 x i64> %y, <2 x i32> %len) {
360360
; CHECK-NEXT: [[T0:%.*]] = sub <2 x i32> <i32 64, i32 64>, [[LEN:%.*]]
361361
; CHECK-NEXT: [[T1:%.*]] = shl <2 x i32> [[X:%.*]], [[T0]]
362362
; CHECK-NEXT: [[T2:%.*]] = add <2 x i32> [[LEN]], <i32 -2, i32 -64>
363-
; CHECK-NEXT: [[T2_WIDE:%.*]] = zext <2 x i32> [[T2]] to <2 x i64>
363+
; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg <2 x i32> [[T2]] to <2 x i64>
364364
; CHECK-NEXT: [[T3:%.*]] = lshr <2 x i64> [[Y:%.*]], [[T2_WIDE]]
365365
; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc <2 x i64> [[T3]] to <2 x i32>
366366
; CHECK-NEXT: [[T4:%.*]] = and <2 x i32> [[T1]], [[T3_TRUNC]]

‎llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-shl.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -400,7 +400,7 @@ define i1 @n13_overshift(i32 %x, i64 %y, i32 %len) {
400400
; CHECK-NEXT: [[T0:%.*]] = sub i32 32, [[LEN:%.*]]
401401
; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[X:%.*]], [[T0]]
402402
; CHECK-NEXT: [[T2:%.*]] = add i32 [[LEN]], 32
403-
; CHECK-NEXT: [[T2_WIDE:%.*]] = zext i32 [[T2]] to i64
403+
; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg i32 [[T2]] to i64
404404
; CHECK-NEXT: [[T3:%.*]] = shl i64 [[Y:%.*]], [[T2_WIDE]]
405405
; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc i64 [[T3]] to i32
406406
; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[T3_TRUNC]]
@@ -421,7 +421,7 @@ define i1 @n13_overshift(i32 %x, i64 %y, i32 %len) {
421421
define i1 @n14_trunc_of_lshr(i64 %x, i32 %y, i32 %len) {
422422
; CHECK-LABEL: @n14_trunc_of_lshr(
423423
; CHECK-NEXT: [[T0:%.*]] = sub i32 32, [[LEN:%.*]]
424-
; CHECK-NEXT: [[T0_WIDE:%.*]] = zext i32 [[T0]] to i64
424+
; CHECK-NEXT: [[T0_WIDE:%.*]] = zext nneg i32 [[T0]] to i64
425425
; CHECK-NEXT: [[T1:%.*]] = lshr i64 [[X:%.*]], [[T0_WIDE]]
426426
; CHECK-NEXT: [[T1_TRUNC:%.*]] = trunc i64 [[T1]] to i32
427427
; CHECK-NEXT: [[T2:%.*]] = add i32 [[LEN]], -1

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