break packed f32 into two f32 regs, not i32 regs

This enables better code simplification.

Author: Prince781

llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp

@@ -190,8 +190,9 @@ void NVPTXDAGToDAGISel::Select(SDNode *N) {
       SelectI128toV2I64(N);
       return;
     }
-    if (N->getOperand(1).getValueType() == MVT::i64 && N->getNumValues() == 3) {
-      SelectI64ToV2I32(N);
+    if (N->getOperand(1).getValueType() == MVT::i64) {
+      // {f32,f32} = mov i64
+      SelectI64ToV2F32(N);
       return;
     }
     break;
@@ -2769,13 +2770,15 @@ void NVPTXDAGToDAGISel::SelectI128toV2I64(SDNode *N) {
   ReplaceNode(N, Mov);
 }
 
-void NVPTXDAGToDAGISel::SelectI64ToV2I32(SDNode *N) {
+void NVPTXDAGToDAGISel::SelectI64ToV2F32(SDNode *N) {
   SDValue Ch = N->getOperand(0);
   SDValue Src = N->getOperand(1);
+  assert(N->getValueType(0) == MVT::f32 && N->getValueType(1) == MVT::f32 &&
+         "expected {f32,f32} = CopyFromReg i64");
   SDLoc DL(N);
 
-  SDNode *Mov = CurDAG->getMachineNode(NVPTX::I64toV2I32, DL,
-                                       {MVT::i32, MVT::i32, Ch.getValueType()},
+  SDNode *Mov = CurDAG->getMachineNode(NVPTX::I64toV2F32, DL,
+                                       {MVT::f32, MVT::f32, Ch.getValueType()},
                                        {Src, Ch});
   ReplaceNode(N, Mov);
 }

llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h

@@ -91,7 +91,7 @@ class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel {
   bool tryEXTRACT_VECTOR_ELEMENT(SDNode *N);
   void SelectV2I64toI128(SDNode *N);
   void SelectI128toV2I64(SDNode *N);
-  void SelectI64ToV2I32(SDNode *N);
+  void SelectI64ToV2F32(SDNode *N);
   void SelectCpAsyncBulkG2S(SDNode *N);
   void SelectCpAsyncBulkS2G(SDNode *N);
   void SelectCpAsyncBulkPrefetchL2(SDNode *N);

llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp

@@ -5638,20 +5638,22 @@ static void ReplaceF32x2Op(SDNode *N, SelectionDAG &DAG,
 
   SDValue Chain = DAG.getEntryNode();
 
-  // break i64 result into two i32 registers for later instructions that may
-  // access element #0 or #1. otherwise, this code will be eliminated
+  // break packed result into two f32 registers for later instructions that may
+  // access element #0 or #1
   SDValue NewValue = DAG.getNode(Opcode, DL, MVT::i64, NewOps);
   MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
   Register DestReg = RegInfo.createVirtualRegister(
       DAG.getTargetLoweringInfo().getRegClassFor(MVT::i64));
   SDValue RegCopy = DAG.getCopyToReg(Chain, DL, DestReg, NewValue);
   SDValue Explode = DAG.getNode(ISD::CopyFromReg, DL,
-                                {MVT::i32, MVT::i32, Chain.getValueType()},
+                                {MVT::f32, MVT::f32, Chain.getValueType()},
                                 {RegCopy, DAG.getRegister(DestReg, MVT::i64)});
   // cast i64 result of new op back to <2 x float>
   Results.push_back(DAG.getBitcast(
-      OldResultTy, DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64,
-                               {Explode.getValue(0), Explode.getValue(1)})));
+      OldResultTy,
+      DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64,
+                  {DAG.getBitcast(MVT::i32, Explode.getValue(0)),
+                   DAG.getBitcast(MVT::i32, Explode.getValue(1))})));
 }
 
 void NVPTXTargetLowering::ReplaceNodeResults(

llvm/lib/Target/NVPTX/NVPTXInstrInfo.td

@@ -3387,6 +3387,9 @@ let hasSideEffects = false in {
   def I64toV2I32 : NVPTXInst<(outs Int32Regs:$d1, Int32Regs:$d2),
                              (ins Int64Regs:$s),
                              "mov.b64 \t{{$d1, $d2}}, $s;", []>;
+  def I64toV2F32 : NVPTXInst<(outs Float32Regs:$d1, Float32Regs:$d2),
+                             (ins Int64Regs:$s),
+                             "mov.b64 \t{{$d1, $d2}}, $s;", []>;
   def I128toV2I64: NVPTXInst<(outs Int64Regs:$d1, Int64Regs:$d2),
                               (ins Int128Regs:$s),
                               "mov.b128 \t{{$d1, $d2}}, $s;", []>;