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--Added support for extension SPV_INTEL_arbitrary_precision_fixed_point
--Added test files for the extension SPV_INTEL_arbitrary_precision_fixed_point
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8 files changed

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‎llvm/docs/SPIRVUsage.rst‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -213,6 +213,8 @@ list of supported SPIR-V extensions, sorted alphabetically by their extension na
213213
- Adds a bitwise instruction on three operands and a look-up table index for specifying the bitwise operation to perform.
214214
* - ``SPV_INTEL_subgroup_matrix_multiply_accumulate``
215215
- Adds an instruction to compute the matrix product of an M x K matrix with a K x N matrix and then add an M x N matrix.
216+
* - ``SPV_INTEL_arbitrary_precision_fixed_point``
217+
- Works without SPV_INTEL_arbitrary_precision_integers, but together they allow greater flexibility in representing arbitrary precision data types.
216218

217219
To enable multiple extensions, list them separated by comma. For example, to enable support for atomic operations on floating-point numbers and arbitrary precision integers, use:
218220

‎llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp‎

Lines changed: 75 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -697,7 +697,8 @@ static bool buildAtomicStoreInst(const SPIRV::IncomingCall *Call,
697697
MachineIRBuilder &MIRBuilder,
698698
SPIRVGlobalRegistry *GR) {
699699
if (Call->isSpirvOp())
700-
return buildOpFromWrapper(MIRBuilder, SPIRV::OpAtomicStore, Call, Register(0));
700+
return buildOpFromWrapper(MIRBuilder, SPIRV::OpAtomicStore, Call,
701+
Register(0));
701702

702703
Register ScopeRegister =
703704
buildConstantIntReg32(SPIRV::Scope::Device, MIRBuilder, GR);
@@ -2307,6 +2308,77 @@ static bool generateBindlessImageINTELInst(const SPIRV::IncomingCall *Call,
23072308
return buildBindlessImageINTELInst(Call, Opcode, MIRBuilder, GR);
23082309
}
23092310

2311+
static bool buildAPFixedPointInst(const SPIRV::IncomingCall *Call,
2312+
unsigned Opcode, MachineIRBuilder &MIRBuilder,
2313+
SPIRVGlobalRegistry *GR) {
2314+
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
2315+
SmallVector<uint32_t, 1> ImmArgs;
2316+
Register InputReg = Call->Arguments[0];
2317+
const Type *RetTy = GR->getTypeForSPIRVType(Call->ReturnType);
2318+
bool IsSRet = RetTy->isVoidTy();
2319+
2320+
if (IsSRet) {
2321+
const LLT ValTy = MRI->getType(InputReg);
2322+
Register ActualRetValReg = MRI->createGenericVirtualRegister(ValTy);
2323+
SPIRVType *InstructionType =
2324+
GR->getPointeeType(GR->getSPIRVTypeForVReg(InputReg));
2325+
InputReg = Call->Arguments[1];
2326+
auto InputType = GR->getTypeForSPIRVType(GR->getSPIRVTypeForVReg(InputReg));
2327+
Register PtrInputReg;
2328+
if (InputType->getTypeID() == llvm::Type::TypeID::TypedPointerTyID) {
2329+
LLT InputLLT = MRI->getType(InputReg);
2330+
PtrInputReg = MRI->createGenericVirtualRegister(InputLLT);
2331+
SPIRVType *PtrType =
2332+
GR->getPointeeType(GR->getSPIRVTypeForVReg(InputReg));
2333+
MachineMemOperand *MMO1 = MIRBuilder.getMF().getMachineMemOperand(
2334+
MachinePointerInfo(), MachineMemOperand::MOLoad,
2335+
InputLLT.getSizeInBytes(), Align(4));
2336+
MIRBuilder.buildLoad(PtrInputReg, InputReg, *MMO1);
2337+
MRI->setRegClass(PtrInputReg, &SPIRV::iIDRegClass);
2338+
GR->assignSPIRVTypeToVReg(PtrType, PtrInputReg, MIRBuilder.getMF());
2339+
}
2340+
2341+
for (unsigned index = 2; index < 7; index++) {
2342+
ImmArgs.push_back(getConstFromIntrinsic(Call->Arguments[index], MRI));
2343+
}
2344+
2345+
// Emit the instruction
2346+
auto MIB = MIRBuilder.buildInstr(Opcode)
2347+
.addDef(ActualRetValReg)
2348+
.addUse(GR->getSPIRVTypeID(InstructionType));
2349+
if (PtrInputReg)
2350+
MIB.addUse(PtrInputReg);
2351+
else
2352+
MIB.addUse(InputReg);
2353+
2354+
for (uint32_t Imm : ImmArgs)
2355+
MIB.addImm(Imm);
2356+
unsigned Size = ValTy.getSizeInBytes();
2357+
// Store result to the pointer passed in Arg[0]
2358+
MachineMemOperand *MMO = MIRBuilder.getMF().getMachineMemOperand(
2359+
MachinePointerInfo(), MachineMemOperand::MOStore, Size, Align(4));
2360+
MRI->setRegClass(ActualRetValReg, &SPIRV::pIDRegClass);
2361+
MIRBuilder.buildStore(ActualRetValReg, Call->Arguments[0], *MMO);
2362+
return true;
2363+
} else {
2364+
for (unsigned index = 1; index < 6; index++)
2365+
ImmArgs.push_back(getConstFromIntrinsic(Call->Arguments[index], MRI));
2366+
2367+
return buildOpFromWrapper(MIRBuilder, Opcode, Call,
2368+
GR->getSPIRVTypeID(Call->ReturnType), ImmArgs);
2369+
}
2370+
}
2371+
2372+
static bool generateAPFixedPointInst(const SPIRV::IncomingCall *Call,
2373+
MachineIRBuilder &MIRBuilder,
2374+
SPIRVGlobalRegistry *GR) {
2375+
const SPIRV::DemangledBuiltin *Builtin = Call->Builtin;
2376+
unsigned Opcode =
2377+
SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode;
2378+
2379+
return buildAPFixedPointInst(Call, Opcode, MIRBuilder, GR);
2380+
}
2381+
23102382
static bool
23112383
generateTernaryBitwiseFunctionINTELInst(const SPIRV::IncomingCall *Call,
23122384
MachineIRBuilder &MIRBuilder,
@@ -2900,6 +2972,8 @@ std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
29002972
return generateExtendedBitOpsInst(Call.get(), MIRBuilder, GR);
29012973
case SPIRV::BindlessINTEL:
29022974
return generateBindlessImageINTELInst(Call.get(), MIRBuilder, GR);
2975+
case SPIRV::ArbitraryPrecisionFixedPoint:
2976+
return generateAPFixedPointInst(Call.get(), MIRBuilder, GR);
29032977
case SPIRV::TernaryBitwiseINTEL:
29042978
return generateTernaryBitwiseFunctionINTELInst(Call.get(), MIRBuilder, GR);
29052979
}

‎llvm/lib/Target/SPIRV/SPIRVBuiltins.td‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -68,6 +68,7 @@ def ICarryBorrow : BuiltinGroup;
6868
def ExtendedBitOps : BuiltinGroup;
6969
def BindlessINTEL : BuiltinGroup;
7070
def TernaryBitwiseINTEL : BuiltinGroup;
71+
def ArbitraryPrecisionFixedPoint : BuiltinGroup;
7172

7273
//===----------------------------------------------------------------------===//
7374
// Class defining a demangled builtin record. The information in the record
@@ -1136,6 +1137,19 @@ defm : DemangledNativeBuiltin<"clock_read_hilo_device", OpenCL_std, KernelClock,
11361137
defm : DemangledNativeBuiltin<"clock_read_hilo_work_group", OpenCL_std, KernelClock, 0, 0, OpReadClockKHR>;
11371138
defm : DemangledNativeBuiltin<"clock_read_hilo_sub_group", OpenCL_std, KernelClock, 0, 0, OpReadClockKHR>;
11381139

1140+
//SPV_INTEL_arbitrary_precision_fixed_point
1141+
defm : DemangledNativeBuiltin<"__spirv_FixedSqrtINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSqrtINTEL>;
1142+
defm : DemangledNativeBuiltin<"__spirv_FixedRecipINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedRecipINTEL>;
1143+
defm : DemangledNativeBuiltin<"__spirv_FixedRsqrtINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedRsqrtINTEL>;
1144+
defm : DemangledNativeBuiltin<"__spirv_FixedSinINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinINTEL>;
1145+
defm : DemangledNativeBuiltin<"__spirv_FixedCosINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedCosINTEL>;
1146+
defm : DemangledNativeBuiltin<"__spirv_FixedSinCosINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinCosINTEL>;
1147+
defm : DemangledNativeBuiltin<"__spirv_FixedSinPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinPiINTEL>;
1148+
defm : DemangledNativeBuiltin<"__spirv_FixedCosPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedCosPiINTEL>;
1149+
defm : DemangledNativeBuiltin<"__spirv_FixedSinCosPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinCosPiINTEL>;
1150+
defm : DemangledNativeBuiltin<"__spirv_FixedLogINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedLogINTEL>;
1151+
defm : DemangledNativeBuiltin<"__spirv_FixedExpINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedExpINTEL>;
1152+
11391153
//===----------------------------------------------------------------------===//
11401154
// Class defining an atomic instruction on floating-point numbers.
11411155
//

‎llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -97,7 +97,10 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
9797
SPIRV::Extension::Extension::
9898
SPV_INTEL_subgroup_matrix_multiply_accumulate},
9999
{"SPV_INTEL_ternary_bitwise_function",
100-
SPIRV::Extension::Extension::SPV_INTEL_ternary_bitwise_function}};
100+
SPIRV::Extension::Extension::SPV_INTEL_ternary_bitwise_function},
101+
{"SPV_INTEL_arbitrary_precision_fixed_point",
102+
SPIRV::Extension::Extension::
103+
SPV_INTEL_arbitrary_precision_fixed_point}};
101104

102105
bool SPIRVExtensionsParser::parse(cl::Option &O, StringRef ArgName,
103106
StringRef ArgValue,

‎llvm/lib/Target/SPIRV/SPIRVInstrInfo.td‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -936,3 +936,27 @@ def OpAliasScopeListDeclINTEL: Op<5913, (outs ID:$res), (ins variable_ops),
936936
// SPV_INTEL_ternary_bitwise_function
937937
def OpBitwiseFunctionINTEL: Op<6242, (outs ID:$res), (ins TYPE:$type, ID:$a, ID:$b, ID:$c, ID:$lut_index),
938938
"$res = OpBitwiseFunctionINTEL $type $a $b $c $lut_index">;
939+
940+
//SPV_INTEL_arbitrary_precision_fixed_point
941+
def OpFixedSqrtINTEL: Op<5923, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
942+
"$res = OpFixedSqrtINTEL $result_type $input $sign $l $rl $q $o">;
943+
def OpFixedRecipINTEL: Op<5924, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
944+
"$res = OpFixedRecipINTEL $result_type $input $sign $l $rl $q $o">;
945+
def OpFixedRsqrtINTEL: Op<5925, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
946+
"$res = OpFixedRsqrtINTEL $result_type $input $sign $l $rl $q $o">;
947+
def OpFixedSinINTEL: Op<5926, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
948+
"$res = OpFixedSinINTEL $result_type $input $sign $l $rl $q $o">;
949+
def OpFixedCosINTEL: Op<5927, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
950+
"$res = OpFixedCosINTEL $result_type $input $sign $l $rl $q $o">;
951+
def OpFixedSinCosINTEL: Op<5928, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
952+
"$res = OpFixedSinCosINTEL $result_type $input $sign $l $rl $q $o">;
953+
def OpFixedSinPiINTEL: Op<5929, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
954+
"$res = OpFixedSinPiINTEL $result_type $input $sign $l $rl $q $o">;
955+
def OpFixedCosPiINTEL: Op<5930, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
956+
"$res = OpFixedCosPiINTEL $result_type $input $sign $l $rl $q $o">;
957+
def OpFixedSinCosPiINTEL: Op<5931, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
958+
"$res = OpFixedSinCosPiINTEL $result_type $input $sign $l $rl $q $o">;
959+
def OpFixedLogINTEL: Op<5932, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
960+
"$res = OpFixedLogINTEL $result_type $input $sign $l $rl $q $o">;
961+
def OpFixedExpINTEL: Op<5933, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
962+
"$res = OpFixedExpINTEL $result_type $input $sign $l $rl $q $o">;

‎llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1516,6 +1516,27 @@ void addInstrRequirements(const MachineInstr &MI,
15161516
Reqs.addCapability(SPIRV::Capability::GroupNonUniformRotateKHR);
15171517
Reqs.addCapability(SPIRV::Capability::GroupNonUniform);
15181518
break;
1519+
case SPIRV::OpFixedCosINTEL:
1520+
case SPIRV::OpFixedSinINTEL:
1521+
case SPIRV::OpFixedCosPiINTEL:
1522+
case SPIRV::OpFixedSinPiINTEL:
1523+
case SPIRV::OpFixedExpINTEL:
1524+
case SPIRV::OpFixedLogINTEL:
1525+
case SPIRV::OpFixedRecipINTEL:
1526+
case SPIRV::OpFixedSqrtINTEL:
1527+
case SPIRV::OpFixedSinCosINTEL:
1528+
case SPIRV::OpFixedSinCosPiINTEL:
1529+
case SPIRV::OpFixedRsqrtINTEL:
1530+
if (!ST.canUseExtension(
1531+
SPIRV::Extension::SPV_INTEL_arbitrary_precision_fixed_point))
1532+
report_fatal_error("This instruction requires the "
1533+
"following SPIR-V extension: "
1534+
"SPV_INTEL_arbitrary_precision_fixed_point",
1535+
false);
1536+
Reqs.addExtension(
1537+
SPIRV::Extension::SPV_INTEL_arbitrary_precision_fixed_point);
1538+
Reqs.addCapability(SPIRV::Capability::ArbitraryPrecisionFixedPointINTEL);
1539+
break;
15191540
case SPIRV::OpGroupIMulKHR:
15201541
case SPIRV::OpGroupFMulKHR:
15211542
case SPIRV::OpGroupBitwiseAndKHR:

‎llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -315,6 +315,7 @@ defm SPV_INTEL_memory_access_aliasing : ExtensionOperand<118>;
315315
defm SPV_INTEL_fp_max_error : ExtensionOperand<119>;
316316
defm SPV_INTEL_ternary_bitwise_function : ExtensionOperand<120>;
317317
defm SPV_INTEL_subgroup_matrix_multiply_accumulate : ExtensionOperand<121>;
318+
defm SPV_INTEL_arbitrary_precision_fixed_point : ExtensionOperand<122>;
318319

319320
//===----------------------------------------------------------------------===//
320321
// Multiclass used to define Capabilities enum values and at the same time
@@ -517,6 +518,7 @@ defm MemoryAccessAliasingINTEL : CapabilityOperand<5910, 0, 0, [SPV_INTEL_memory
517518
defm FPMaxErrorINTEL : CapabilityOperand<6169, 0, 0, [SPV_INTEL_fp_max_error], []>;
518519
defm TernaryBitwiseFunctionINTEL : CapabilityOperand<6241, 0, 0, [SPV_INTEL_ternary_bitwise_function], []>;
519520
defm SubgroupMatrixMultiplyAccumulateINTEL : CapabilityOperand<6236, 0, 0, [SPV_INTEL_subgroup_matrix_multiply_accumulate], []>;
521+
defm ArbitraryPrecisionFixedPointINTEL : CapabilityOperand<5922, 0, 0, [SPV_INTEL_arbitrary_precision_fixed_point], []>;
520522

521523
//===----------------------------------------------------------------------===//
522524
// Multiclass used to define SourceLanguage enum values and at the same time

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