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[clang-format] Recognize Verilog export and import
The directives should not change the indentation level. Previously the program erroneously added an indentation level when it saw the `function` keyword.
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4 files changed

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-51
lines changed

4 files changed

+179
-51
lines changed

‎clang/lib/Format/FormatToken.h‎

Lines changed: 137 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -1164,6 +1164,7 @@ struct AdditionalKeywords {
11641164
kw_checker = &IdentTable.get("checker");
11651165
kw_clocking = &IdentTable.get("clocking");
11661166
kw_constraint = &IdentTable.get("constraint");
1167+
kw_context = &IdentTable.get("context");
11671168
kw_cover = &IdentTable.get("cover");
11681169
kw_covergroup = &IdentTable.get("covergroup");
11691170
kw_coverpoint = &IdentTable.get("coverpoint");
@@ -1319,50 +1320,138 @@ struct AdditionalKeywords {
13191320
// Some keywords are not included here because they don't need special
13201321
// treatment like `showcancelled` or they should be treated as identifiers
13211322
// like `int` and `logic`.
1322-
VerilogExtraKeywords = std::unordered_set<IdentifierInfo *>(
1323-
{kw_always, kw_always_comb, kw_always_ff,
1324-
kw_always_latch, kw_assert, kw_assign,
1325-
kw_assume, kw_automatic, kw_before,
1326-
kw_begin, kw_bins, kw_binsof,
1327-
kw_casex, kw_casez, kw_celldefine,
1328-
kw_checker, kw_clocking, kw_constraint,
1329-
kw_cover, kw_covergroup, kw_coverpoint,
1330-
kw_disable, kw_dist, kw_edge,
1331-
kw_end, kw_endcase, kw_endchecker,
1332-
kw_endclass, kw_endclocking, kw_endfunction,
1333-
kw_endgenerate, kw_endgroup, kw_endinterface,
1334-
kw_endmodule, kw_endpackage, kw_endprimitive,
1335-
kw_endprogram, kw_endproperty, kw_endsequence,
1336-
kw_endspecify, kw_endtable, kw_endtask,
1337-
kw_extends, kw_final, kw_foreach,
1338-
kw_forever, kw_fork, kw_function,
1339-
kw_generate, kw_highz0, kw_highz1,
1340-
kw_iff, kw_ifnone, kw_ignore_bins,
1341-
kw_illegal_bins, kw_implements, kw_import,
1342-
kw_initial, kw_inout, kw_input,
1343-
kw_inside, kw_interconnect, kw_interface,
1344-
kw_intersect, kw_join, kw_join_any,
1345-
kw_join_none, kw_large, kw_let,
1346-
kw_local, kw_localparam, kw_macromodule,
1347-
kw_matches, kw_medium, kw_negedge,
1348-
kw_output, kw_package, kw_packed,
1349-
kw_parameter, kw_posedge, kw_primitive,
1350-
kw_priority, kw_program, kw_property,
1351-
kw_pull0, kw_pull1, kw_pure,
1352-
kw_rand, kw_randc, kw_randcase,
1353-
kw_randsequence, kw_ref, kw_repeat,
1354-
kw_sample, kw_scalared, kw_sequence,
1355-
kw_small, kw_soft, kw_solve,
1356-
kw_specify, kw_specparam, kw_strong0,
1357-
kw_strong1, kw_supply0, kw_supply1,
1358-
kw_table, kw_tagged, kw_task,
1359-
kw_tri, kw_tri0, kw_tri1,
1360-
kw_triand, kw_trior, kw_trireg,
1361-
kw_unique, kw_unique0, kw_uwire,
1362-
kw_var, kw_vectored, kw_wait,
1363-
kw_wand, kw_weak0, kw_weak1,
1364-
kw_wildcard, kw_wire, kw_with,
1365-
kw_wor, kw_verilogHash, kw_verilogHashHash});
1323+
VerilogExtraKeywords =
1324+
std::unordered_set<IdentifierInfo *>({kw_always,
1325+
kw_always_comb,
1326+
kw_always_ff,
1327+
kw_always_latch,
1328+
kw_assert,
1329+
kw_assign,
1330+
kw_assume,
1331+
kw_automatic,
1332+
kw_before,
1333+
kw_begin,
1334+
kw_bins,
1335+
kw_binsof,
1336+
kw_casex,
1337+
kw_casez,
1338+
kw_celldefine,
1339+
kw_checker,
1340+
kw_clocking,
1341+
kw_constraint,
1342+
kw_context,
1343+
kw_cover,
1344+
kw_covergroup,
1345+
kw_coverpoint,
1346+
kw_disable,
1347+
kw_dist,
1348+
kw_edge,
1349+
kw_end,
1350+
kw_endcase,
1351+
kw_endchecker,
1352+
kw_endclass,
1353+
kw_endclocking,
1354+
kw_endfunction,
1355+
kw_endgenerate,
1356+
kw_endgroup,
1357+
kw_endinterface,
1358+
kw_endmodule,
1359+
kw_endpackage,
1360+
kw_endprimitive,
1361+
kw_endprogram,
1362+
kw_endproperty,
1363+
kw_endsequence,
1364+
kw_endspecify,
1365+
kw_endtable,
1366+
kw_endtask,
1367+
kw_extends,
1368+
kw_final,
1369+
kw_foreach,
1370+
kw_forever,
1371+
kw_fork,
1372+
kw_function,
1373+
kw_generate,
1374+
kw_highz0,
1375+
kw_highz1,
1376+
kw_iff,
1377+
kw_ifnone,
1378+
kw_ignore_bins,
1379+
kw_illegal_bins,
1380+
kw_implements,
1381+
kw_import,
1382+
kw_initial,
1383+
kw_inout,
1384+
kw_input,
1385+
kw_inside,
1386+
kw_interconnect,
1387+
kw_interface,
1388+
kw_intersect,
1389+
kw_join,
1390+
kw_join_any,
1391+
kw_join_none,
1392+
kw_large,
1393+
kw_let,
1394+
kw_local,
1395+
kw_localparam,
1396+
kw_macromodule,
1397+
kw_matches,
1398+
kw_medium,
1399+
kw_module,
1400+
kw_negedge,
1401+
kw_output,
1402+
kw_package,
1403+
kw_packed,
1404+
kw_parameter,
1405+
kw_posedge,
1406+
kw_primitive,
1407+
kw_priority,
1408+
kw_program,
1409+
kw_property,
1410+
kw_pull0,
1411+
kw_pull1,
1412+
kw_pure,
1413+
kw_rand,
1414+
kw_randc,
1415+
kw_randcase,
1416+
kw_randsequence,
1417+
kw_ref,
1418+
kw_repeat,
1419+
kw_sample,
1420+
kw_scalared,
1421+
kw_sequence,
1422+
kw_small,
1423+
kw_soft,
1424+
kw_solve,
1425+
kw_specify,
1426+
kw_specparam,
1427+
kw_strong0,
1428+
kw_strong1,
1429+
kw_supply0,
1430+
kw_supply1,
1431+
kw_table,
1432+
kw_tagged,
1433+
kw_task,
1434+
kw_tri,
1435+
kw_tri0,
1436+
kw_tri1,
1437+
kw_triand,
1438+
kw_trior,
1439+
kw_trireg,
1440+
kw_unique,
1441+
kw_unique0,
1442+
kw_uwire,
1443+
kw_var,
1444+
kw_vectored,
1445+
kw_wait,
1446+
kw_wand,
1447+
kw_weak0,
1448+
kw_weak1,
1449+
kw_wildcard,
1450+
kw_wire,
1451+
kw_with,
1452+
kw_wor,
1453+
kw_verilogHash,
1454+
kw_verilogHashHash});
13661455

13671456
TableGenExtraKeywords = std::unordered_set<IdentifierInfo *>({
13681457
kw_assert,
@@ -1510,6 +1599,7 @@ struct AdditionalKeywords {
15101599
IdentifierInfo *kw_checker;
15111600
IdentifierInfo *kw_clocking;
15121601
IdentifierInfo *kw_constraint;
1602+
IdentifierInfo *kw_context;
15131603
IdentifierInfo *kw_cover;
15141604
IdentifierInfo *kw_covergroup;
15151605
IdentifierInfo *kw_coverpoint;
@@ -1794,11 +1884,13 @@ struct AdditionalKeywords {
17941884
case tok::kw_continue:
17951885
case tok::kw_default:
17961886
case tok::kw_do:
1797-
case tok::kw_extern:
17981887
case tok::kw_else:
17991888
case tok::kw_enum:
1889+
case tok::kw_export:
1890+
case tok::kw_extern:
18001891
case tok::kw_for:
18011892
case tok::kw_if:
1893+
case tok::kw_import:
18021894
case tok::kw_restrict:
18031895
case tok::kw_signed:
18041896
case tok::kw_static:

‎clang/lib/Format/UnwrappedLineParser.cpp‎

Lines changed: 30 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1588,15 +1588,15 @@ void UnwrappedLineParser::parseStructuralElement(
15881588
parseTryCatch();
15891589
return;
15901590
case tok::kw_extern:
1591-
nextToken();
15921591
if (Style.isVerilog()) {
1593-
// In Verilog and extern module declaration looks like a start of module.
1592+
// In Verilog an extern module declaration looks like a start of module.
15941593
// But there is no body and endmodule. So we handle it separately.
1595-
if (Keywords.isVerilogHierarchy(*FormatTok)) {
1596-
parseVerilogHierarchyHeader();
1594+
if (tryToParseVerilogExtern())
15971595
return;
1598-
}
1599-
} else if (FormatTok->is(tok::string_literal)) {
1596+
break;
1597+
}
1598+
nextToken();
1599+
if (FormatTok->is(tok::string_literal)) {
16001600
nextToken();
16011601
if (FormatTok->is(tok::l_brace)) {
16021602
if (Style.BraceWrapping.AfterExternBlock)
@@ -1621,6 +1621,8 @@ void UnwrappedLineParser::parseStructuralElement(
16211621
parseJavaScriptEs6ImportExport();
16221622
return;
16231623
}
1624+
if (Style.isVerilog() && tryToParseVerilogExtern())
1625+
return;
16241626
if (IsCpp) {
16251627
nextToken();
16261628
if (FormatTok->is(tok::kw_namespace)) {
@@ -1669,6 +1671,8 @@ void UnwrappedLineParser::parseStructuralElement(
16691671
addUnwrappedLine();
16701672
return;
16711673
}
1674+
if (Style.isVerilog() && tryToParseVerilogExtern())
1675+
return;
16721676
if (IsCpp && parseModuleImport())
16731677
return;
16741678
}
@@ -4555,6 +4559,26 @@ void UnwrappedLineParser::parseVerilogCaseLabel() {
45554559
Line->Level = OrigLevel;
45564560
}
45574561

4562+
bool UnwrappedLineParser::tryToParseVerilogExtern() {
4563+
assert(
4564+
FormatTok->isOneOf(tok::kw_extern, tok::kw_export, Keywords.kw_import));
4565+
nextToken();
4566+
// "DPI-C"
4567+
if (FormatTok->is(tok::string_literal))
4568+
nextToken();
4569+
if (FormatTok->isOneOf(Keywords.kw_context, Keywords.kw_pure))
4570+
nextToken();
4571+
if (Keywords.isVerilogIdentifier(*FormatTok))
4572+
nextToken();
4573+
if (FormatTok->is(tok::equal))
4574+
nextToken();
4575+
if (Keywords.isVerilogHierarchy(*FormatTok)) {
4576+
parseVerilogHierarchyHeader();
4577+
return true;
4578+
}
4579+
return false;
4580+
}
4581+
45584582
bool UnwrappedLineParser::containsExpansion(const UnwrappedLine &Line) const {
45594583
for (const auto &N : Line.Tokens) {
45604584
if (N.Tok->MacroCtx)

‎clang/lib/Format/UnwrappedLineParser.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -205,6 +205,8 @@ class UnwrappedLineParser {
205205
unsigned parseVerilogHierarchyHeader();
206206
void parseVerilogTable();
207207
void parseVerilogCaseLabel();
208+
// For import, export, and extern.
209+
bool tryToParseVerilogExtern();
208210
std::optional<llvm::SmallVector<llvm::SmallVector<FormatToken *, 8>, 1>>
209211
parseMacroCall();
210212

‎clang/unittests/Format/FormatTestVerilog.cpp‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -676,6 +676,16 @@ TEST_F(FormatTestVerilog, Hierarchy) {
676676
" endprogram\n"
677677
"endmodule");
678678
// Test that an extern declaration doesn't change the indentation.
679+
verifyFormat("import \"DPI-C\" context MyCFunc = function integer MapID\n"
680+
" (int portID);\n"
681+
"x = x;");
682+
verifyFormat("export \"DPI-C\" function exported_sv_func;\n"
683+
"x = x;");
684+
verifyFormat("import \"DPI-C\" function void f1\n"
685+
" (input int i1,\n"
686+
" pair i2,\n"
687+
" output logic [63 : 0] o3);\n"
688+
"x = x;");
679689
verifyFormat("extern module x;\n"
680690
"x = x;");
681691
// Test complex headers

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