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nikicnikic
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[CodeGen] Use getSignedConstant() in more places
Use getSignedConstant() in a few more places, based on a search of `\bgetConstant(-`. Most of these were fine as-is (e.g. because they work on 64-bits), but I think it's better to use getSignedConstant() consistently for negative numbers.
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6 files changed

+32
-28
lines changed

6 files changed

+32
-28
lines changed

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp‎

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -11780,8 +11780,9 @@ SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
1178011780
if (Align && *Align > MinSlotSize) {
1178111781
VAList = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
1178211782
DAG.getConstant(Align->value() - 1, DL, PtrVT));
11783-
VAList = DAG.getNode(ISD::AND, DL, PtrVT, VAList,
11784-
DAG.getConstant(-(int64_t)Align->value(), DL, PtrVT));
11783+
VAList =
11784+
DAG.getNode(ISD::AND, DL, PtrVT, VAList,
11785+
DAG.getSignedConstant(-(int64_t)Align->value(), DL, PtrVT));
1178511786
}
1178611787

1178711788
Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
@@ -16147,8 +16148,9 @@ AArch64TargetLowering::LowerWindowsDYNAMIC_STACKALLOC(SDValue Op,
1614716148
Chain = SP.getValue(1);
1614816149
SP = DAG.getNode(ISD::SUB, dl, MVT::i64, SP, Size);
1614916150
if (Align)
16150-
SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16151-
DAG.getConstant(-(uint64_t)Align->value(), dl, VT));
16151+
SP =
16152+
DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16153+
DAG.getSignedConstant(-(uint64_t)Align->value(), dl, VT));
1615216154
Chain = DAG.getCopyToReg(Chain, dl, AArch64::SP, SP);
1615316155
SDValue Ops[2] = {SP, Chain};
1615416156
return DAG.getMergeValues(Ops, dl);
@@ -16185,7 +16187,7 @@ AArch64TargetLowering::LowerWindowsDYNAMIC_STACKALLOC(SDValue Op,
1618516187
SP = DAG.getNode(ISD::SUB, dl, MVT::i64, SP, Size);
1618616188
if (Align)
1618716189
SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16188-
DAG.getConstant(-(uint64_t)Align->value(), dl, VT));
16190+
DAG.getSignedConstant(-(uint64_t)Align->value(), dl, VT));
1618916191
Chain = DAG.getCopyToReg(Chain, dl, AArch64::SP, SP);
1619016192

1619116193
Chain = DAG.getCALLSEQ_END(Chain, 0, 0, SDValue(), dl);
@@ -16213,7 +16215,7 @@ AArch64TargetLowering::LowerInlineDYNAMIC_STACKALLOC(SDValue Op,
1621316215
SP = DAG.getNode(ISD::SUB, dl, MVT::i64, SP, Size);
1621416216
if (Align)
1621516217
SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16216-
DAG.getConstant(-(uint64_t)Align->value(), dl, VT));
16218+
DAG.getSignedConstant(-(uint64_t)Align->value(), dl, VT));
1621716219

1621816220
// Set the real SP to the new value with a probing loop.
1621916221
Chain = DAG.getNode(AArch64ISD::PROBED_ALLOCA, dl, MVT::Other, Chain, SP);
@@ -21485,7 +21487,7 @@ static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
2148521487

2148621488
if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits) {
2148721489
Op = DAG.getNode(Opcode, dl, VT, Op,
21488-
DAG.getConstant(-ShiftAmount, dl, MVT::i32));
21490+
DAG.getSignedConstant(-ShiftAmount, dl, MVT::i32));
2148921491
if (N->getValueType(0) == MVT::i64)
2149021492
Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Op,
2149121493
DAG.getConstant(0, dl, MVT::i64));
@@ -27364,10 +27366,10 @@ static void ReplaceATOMIC_LOAD_128Results(SDNode *N,
2736427366
SDLoc dl(Val128);
2736527367
Val2x64.first =
2736627368
DAG.getNode(ISD::XOR, dl, MVT::i64,
27367-
DAG.getConstant(-1ULL, dl, MVT::i64), Val2x64.first);
27369+
DAG.getAllOnesConstant(dl, MVT::i64), Val2x64.first);
2736827370
Val2x64.second =
2736927371
DAG.getNode(ISD::XOR, dl, MVT::i64,
27370-
DAG.getConstant(-1ULL, dl, MVT::i64), Val2x64.second);
27372+
DAG.getAllOnesConstant(dl, MVT::i64), Val2x64.second);
2737127373
}
2737227374

2737327375
SDValue Ops[] = {Val2x64.first, Val2x64.second, Ptr, Chain};

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -913,7 +913,7 @@ class VGPRImm <dag frag> : PatLeaf<frag, [{
913913
}
914914

915915
def NegateImm : SDNodeXForm<imm, [{
916-
return CurDAG->getConstant(-N->getSExtValue(), SDLoc(N), MVT::i32);
916+
return CurDAG->getSignedConstant(-N->getSExtValue(), SDLoc(N), MVT::i32);
917917
}]>;
918918

919919
// TODO: When FP inline imm values work?

‎llvm/lib/Target/ARM/ARMISelLowering.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -20786,9 +20786,9 @@ ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
2078620786
Chain = SP.getValue(1);
2078720787
SP = DAG.getNode(ISD::SUB, DL, MVT::i32, SP, Size);
2078820788
if (Align)
20789-
SP =
20790-
DAG.getNode(ISD::AND, DL, MVT::i32, SP.getValue(0),
20791-
DAG.getConstant(-(uint64_t)Align->value(), DL, MVT::i32));
20789+
SP = DAG.getNode(
20790+
ISD::AND, DL, MVT::i32, SP.getValue(0),
20791+
DAG.getSignedConstant(-(uint64_t)Align->value(), DL, MVT::i32));
2079220792
Chain = DAG.getCopyToReg(Chain, DL, ARM::SP, SP);
2079320793
SDValue Ops[2] = { SP, Chain };
2079420794
return DAG.getMergeValues(Ops, DL);

‎llvm/lib/Target/Hexagon/HexagonISelLowering.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3491,7 +3491,7 @@ HexagonTargetLowering::PerformDAGCombine(SDNode *N,
34913491
SDValue P = Op.getOperand(0);
34923492
switch (P.getOpcode()) {
34933493
case HexagonISD::PTRUE:
3494-
return DCI.DAG.getConstant(-1, dl, ty(Op));
3494+
return DCI.DAG.getAllOnesConstant(dl, ty(Op));
34953495
case HexagonISD::PFALSE:
34963496
return getZero(dl, ty(Op), DCI.DAG);
34973497
default:

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -8883,8 +8883,8 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
88838883
Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
88848884
Round, DAG.getConstant(2047, dl, MVT::i64));
88858885
Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
8886-
Round = DAG.getNode(ISD::AND, dl, MVT::i64,
8887-
Round, DAG.getConstant(-2048, dl, MVT::i64));
8886+
Round = DAG.getNode(ISD::AND, dl, MVT::i64, Round,
8887+
DAG.getSignedConstant(-2048, dl, MVT::i64));
88888888

88898889
// However, we cannot use that value unconditionally: if the magnitude
88908890
// of the input value is small, the bit-twiddling we did above might
@@ -9244,7 +9244,7 @@ SDValue PPCTargetLowering::LowerGET_ROUNDING(SDValue Op,
92449244

92459245
SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
92469246
EVT VT = Op.getValueType();
9247-
unsigned BitWidth = VT.getSizeInBits();
9247+
uint64_t BitWidth = VT.getSizeInBits();
92489248
SDLoc dl(Op);
92499249
assert(Op.getNumOperands() == 3 &&
92509250
VT == Op.getOperand(1).getValueType() &&
@@ -9263,7 +9263,7 @@ SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
92639263
SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
92649264
SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
92659265
SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
9266-
DAG.getConstant(-BitWidth, dl, AmtVT));
9266+
DAG.getSignedConstant(-BitWidth, dl, AmtVT));
92679267
SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
92689268
SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
92699269
SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
@@ -9274,7 +9274,7 @@ SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
92749274
SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
92759275
EVT VT = Op.getValueType();
92769276
SDLoc dl(Op);
9277-
unsigned BitWidth = VT.getSizeInBits();
9277+
uint64_t BitWidth = VT.getSizeInBits();
92789278
assert(Op.getNumOperands() == 3 &&
92799279
VT == Op.getOperand(1).getValueType() &&
92809280
"Unexpected SRL!");
@@ -9292,7 +9292,7 @@ SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
92929292
SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
92939293
SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
92949294
SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
9295-
DAG.getConstant(-BitWidth, dl, AmtVT));
9295+
DAG.getSignedConstant(-BitWidth, dl, AmtVT));
92969296
SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
92979297
SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
92989298
SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
@@ -9303,7 +9303,7 @@ SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
93039303
SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
93049304
SDLoc dl(Op);
93059305
EVT VT = Op.getValueType();
9306-
unsigned BitWidth = VT.getSizeInBits();
9306+
uint64_t BitWidth = VT.getSizeInBits();
93079307
assert(Op.getNumOperands() == 3 &&
93089308
VT == Op.getOperand(1).getValueType() &&
93099309
"Unexpected SRA!");
@@ -9320,7 +9320,7 @@ SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
93209320
SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
93219321
SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
93229322
SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
9323-
DAG.getConstant(-BitWidth, dl, AmtVT));
9323+
DAG.getSignedConstant(-BitWidth, dl, AmtVT));
93249324
SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
93259325
SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
93269326
SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, dl, AmtVT),
@@ -18308,7 +18308,7 @@ static SDValue combineADDToADDZE(SDNode *N, SelectionDAG &DAG,
1830818308
SDValue AddOrZ = NegConstant != 0 ? Add : Z;
1830918309
SDValue Addc =
1831018310
DAG.getNode(ISD::UADDO_CARRY, DL, DAG.getVTList(MVT::i64, CarryType),
18311-
AddOrZ, DAG.getConstant(-1ULL, DL, MVT::i64),
18311+
AddOrZ, DAG.getAllOnesConstant(DL, MVT::i64),
1831218312
DAG.getConstant(0, DL, CarryType));
1831318313
return DAG.getNode(ISD::UADDO_CARRY, DL, VTs, LHS,
1831418314
DAG.getConstant(0, DL, MVT::i64),

‎llvm/lib/Target/VE/VEISelLowering.cpp‎

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1216,8 +1216,9 @@ SDValue VETargetLowering::lowerATOMIC_SWAP(SDValue Op,
12161216
SDValue NewVal = prepareTS1AM(Op, DAG, Flag, Bits);
12171217

12181218
SDValue Ptr = N->getOperand(1);
1219-
SDValue Aligned = DAG.getNode(ISD::AND, DL, Ptr.getValueType(),
1220-
{Ptr, DAG.getConstant(-4, DL, MVT::i64)});
1219+
SDValue Aligned =
1220+
DAG.getNode(ISD::AND, DL, Ptr.getValueType(),
1221+
{Ptr, DAG.getSignedConstant(-4, DL, MVT::i64)});
12211222
SDValue TS1AM = DAG.getAtomic(VEISD::TS1AM, DL, N->getMemoryVT(),
12221223
DAG.getVTList(Op.getNode()->getValueType(0),
12231224
Op.getNode()->getValueType(1)),
@@ -1235,8 +1236,9 @@ SDValue VETargetLowering::lowerATOMIC_SWAP(SDValue Op,
12351236
SDValue NewVal = prepareTS1AM(Op, DAG, Flag, Bits);
12361237

12371238
SDValue Ptr = N->getOperand(1);
1238-
SDValue Aligned = DAG.getNode(ISD::AND, DL, Ptr.getValueType(),
1239-
{Ptr, DAG.getConstant(-4, DL, MVT::i64)});
1239+
SDValue Aligned =
1240+
DAG.getNode(ISD::AND, DL, Ptr.getValueType(),
1241+
{Ptr, DAG.getSignedConstant(-4, DL, MVT::i64)});
12401242
SDValue TS1AM = DAG.getAtomic(VEISD::TS1AM, DL, N->getMemoryVT(),
12411243
DAG.getVTList(Op.getNode()->getValueType(0),
12421244
Op.getNode()->getValueType(1)),
@@ -1601,7 +1603,7 @@ SDValue VETargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16011603
VAList = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
16021604
DAG.getConstant(Align - 1, DL, PtrVT));
16031605
VAList = DAG.getNode(ISD::AND, DL, PtrVT, VAList,
1604-
DAG.getConstant(-Align, DL, PtrVT));
1606+
DAG.getSignedConstant(-Align, DL, PtrVT));
16051607
// Increment the pointer, VAList, by 16 to the next vaarg.
16061608
NextPtr =
16071609
DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getIntPtrConstant(16, DL));

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