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topperctopperc
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fixup! Address review comments
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3 files changed

+69
-96
lines changed

3 files changed

+69
-96
lines changed

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp‎

Lines changed: 33 additions & 57 deletions
Original file line numberDiff line numberDiff line change
@@ -77,12 +77,6 @@ class RISCVAsmParser : public MCTargetAsmParser {
7777
VTypeState_Done,
7878
};
7979

80-
enum WWEEState {
81-
WWEEState_Widen,
82-
WWEEState_SEW,
83-
WWEEState_Done,
84-
};
85-
8680
SmallVector<FeatureBitset, 4> FeatureBitStack;
8781

8882
SmallVector<ParserOptionsSet, 4> ParserOptionsStack;
@@ -131,8 +125,6 @@ class RISCVAsmParser : public MCTargetAsmParser {
131125
bool &MaskAgnostic);
132126
bool generateVTypeError(SMLoc ErrorLoc);
133127

134-
bool parseXSfmmVTypeToken(const AsmToken &Tok, WWEEState &State, unsigned &WW,
135-
unsigned &EE, bool &AltFmt);
136128
bool generateXSfmmVTypeError(SMLoc ErrorLoc);
137129
// Helper to actually emit an instruction to the MCStreamer. Also, when
138130
// possible, compression of the instruction is performed.
@@ -2316,74 +2308,58 @@ bool RISCVAsmParser::generateVTypeError(SMLoc ErrorLoc) {
23162308
"e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]");
23172309
}
23182310

2319-
bool RISCVAsmParser::parseXSfmmVTypeToken(const AsmToken &Tok, WWEEState &State,
2320-
unsigned &WW, unsigned &EE,
2321-
bool &AltFmt) {
2322-
if (getLexer().isNot(AsmToken::Identifier))
2323-
return true;
2324-
2325-
StringRef Identifier = getTok().getIdentifier();
2326-
2327-
switch (State) {
2328-
case WWEEState_SEW:
2329-
if (!Identifier.consume_front("e"))
2330-
break;
2331-
if (Identifier.getAsInteger(10, EE)) {
2332-
if (Identifier != "16alt")
2333-
break;
2334-
2335-
AltFmt = true;
2336-
EE = 16;
2337-
}
2338-
if (!RISCVVType::isValidSEW(EE))
2339-
break;
2340-
State = WWEEState_Widen;
2341-
return false;
2342-
case WWEEState_Widen:
2343-
if (!Identifier.consume_front("w"))
2344-
break;
2345-
if (Identifier.getAsInteger(10, WW))
2346-
break;
2347-
if (WW != 1 && WW != 2 && WW != 4)
2348-
break;
2349-
State = WWEEState_Done;
2350-
return false;
2351-
case WWEEState_Done:
2352-
// Extra token?
2353-
break;
2354-
}
2355-
2356-
return true;
2357-
}
2358-
23592311
ParseStatus RISCVAsmParser::parseXSfmmVType(OperandVector &Operands) {
23602312
SMLoc S = getLoc();
23612313

23622314
unsigned Widen = 0;
23632315
unsigned SEW = 0;
23642316
bool AltFmt = false;
2317+
StringRef Identifier;
23652318

2366-
WWEEState State = WWEEState_SEW;
2319+
if (getTok().isNot(AsmToken::Identifier))
2320+
goto Fail;
23672321

2368-
if (parseXSfmmVTypeToken(getTok(), State, Widen, SEW, AltFmt))
2369-
return generateXSfmmVTypeError(S);
2322+
Identifier = getTok().getIdentifier();
23702323

2371-
getLexer().Lex();
2324+
if (!Identifier.consume_front("e"))
2325+
goto Fail;
2326+
2327+
if (Identifier.getAsInteger(10, SEW)) {
2328+
if (Identifier != "16alt")
2329+
goto Fail;
2330+
2331+
AltFmt = true;
2332+
SEW = 16;
2333+
}
2334+
if (!RISCVVType::isValidSEW(SEW))
2335+
goto Fail;
2336+
2337+
Lex();
23722338

23732339
if (!parseOptionalToken(AsmToken::Comma))
2374-
return generateXSfmmVTypeError(S);
2340+
goto Fail;
23752341

2376-
if (parseXSfmmVTypeToken(getTok(), State, Widen, SEW, AltFmt))
2377-
return generateXSfmmVTypeError(S);
2342+
if (getTok().isNot(AsmToken::Identifier))
2343+
goto Fail;
23782344

2379-
getLexer().Lex();
2345+
Identifier = getTok().getIdentifier();
23802346

2381-
if (getLexer().is(AsmToken::EndOfStatement) && State == WWEEState_Done) {
2347+
if (!Identifier.consume_front("w"))
2348+
goto Fail;
2349+
if (Identifier.getAsInteger(10, Widen))
2350+
goto Fail;
2351+
if (Widen != 1 && Widen != 2 && Widen != 4)
2352+
goto Fail;
2353+
2354+
Lex();
2355+
2356+
if (getLexer().is(AsmToken::EndOfStatement)) {
23822357
Operands.push_back(RISCVOperand::createVType(
23832358
RISCVVType::encodeXSfmmVType(SEW, Widen, AltFmt), S));
23842359
return ParseStatus::Success;
23852360
}
23862361

2362+
Fail:
23872363
return generateXSfmmVTypeError(S);
23882364
}
23892365

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -744,9 +744,9 @@ static constexpr FeatureBitset XqciFeatureGroup = {
744744
};
745745

746746
static constexpr FeatureBitset XSfVectorGroup = {
747-
RISCV::FeatureVendorXSfvcp, RISCV::FeatureVendorXSfvqmaccdod,
748-
RISCV::FeatureVendorXSfvqmaccqoq, RISCV::FeatureVendorXSfvfwmaccqqq,
749-
RISCV::FeatureVendorXSfvfnrclipxfqf};
747+
RISCV::FeatureVendorXSfvcp, RISCV::FeatureVendorXSfvqmaccdod,
748+
RISCV::FeatureVendorXSfvqmaccqoq, RISCV::FeatureVendorXSfvfwmaccqqq,
749+
RISCV::FeatureVendorXSfvfnrclipxfqf, RISCV::FeatureVendorXSfmmbase};
750750
static constexpr FeatureBitset XSfSystemGroup = {
751751
RISCV::FeatureVendorXSiFivecdiscarddlone,
752752
RISCV::FeatureVendorXSiFivecflushdlone,
@@ -767,7 +767,6 @@ static constexpr DecoderListEntry DecoderList32[]{
767767
"XVentanaCondOps"},
768768
{DecoderTableXTHead32, XTHeadGroup, "T-Head extensions"},
769769
{DecoderTableXSfvector32, XSfVectorGroup, "SiFive vector extensions"},
770-
{DecoderTableXSfmm32, {RISCV::FeatureVendorXSfmmbase}, "SiFive XSfmm"},
771770
{DecoderTableXSfsystem32, XSfSystemGroup, "SiFive system extensions"},
772771
{DecoderTableXSfcease32, {RISCV::FeatureVendorXSfcease}, "SiFive sf.cease"},
773772
{DecoderTableXmipslsp32, {RISCV::FeatureVendorXMIPSLSP}, "MIPS mips.lsp"},

‎llvm/lib/Target/RISCV/RISCVInstrInfoXSfmm.td‎

Lines changed: 33 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ def XSfmmVTypeOp : RISCVOp {
3232
}
3333

3434
let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
35-
class RVInstSetSingle<dag outs, dag ins, bits<5> rs2, string opcodestr,
35+
class SFInstSetSingle<dag outs, dag ins, bits<5> rs2, string opcodestr,
3636
string argstr>
3737
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
3838
bits<5> rs1;
@@ -48,7 +48,7 @@ class RVInstSetSingle<dag outs, dag ins, bits<5> rs2, string opcodestr,
4848
let Defs = [VTYPE, VL];
4949
}
5050

51-
class RVInstTileMemOp<dag outs, dag ins, bits<3> nf, RISCVOpcode opcode,
51+
class SFInstTileMemOp<dag outs, dag ins, bits<3> nf, RISCVOpcode opcode,
5252
string opcodestr, string argstr>
5353
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
5454
bits<5> rs2;
@@ -68,17 +68,17 @@ class RVInstTileMemOp<dag outs, dag ins, bits<3> nf, RISCVOpcode opcode,
6868
}
6969

7070
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
71-
class RVInstTileLoad<bits<3> nf, string opcodestr>
72-
: RVInstTileMemOp<(outs), (ins GPR:$rs2, GPRMemZeroOffset:$rs1), nf,
71+
class SFInstTileLoad<bits<3> nf, string opcodestr>
72+
: SFInstTileMemOp<(outs), (ins GPR:$rs2, GPRMemZeroOffset:$rs1), nf,
7373
OPC_LOAD_FP, opcodestr, "$rs2, ${rs1}">;
7474

7575
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
76-
class RVInstTileStore<bits<3> nf, string opcodestr>
77-
: RVInstTileMemOp<(outs), (ins GPR:$rs2, GPRMemZeroOffset:$rs1), nf,
76+
class SFInstTileStore<bits<3> nf, string opcodestr>
77+
: SFInstTileMemOp<(outs), (ins GPR:$rs2, GPRMemZeroOffset:$rs1), nf,
7878
OPC_STORE_FP, opcodestr, "$rs2, ${rs1}">;
7979

8080
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
81-
class RVInstTileMoveOp<bits<6> funct6, dag outs, dag ins, string opcodestr,
81+
class SFInstTileMoveOp<bits<6> funct6, dag outs, dag ins, string opcodestr,
8282
string argstr>
8383
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
8484
bits<5> rs2;
@@ -97,7 +97,7 @@ class RVInstTileMoveOp<bits<6> funct6, dag outs, dag ins, string opcodestr,
9797
}
9898

9999
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
100-
class RVInstMatmulF<dag outs, dag ins, string opcodestr, string argstr>
100+
class SFInstMatmulF<dag outs, dag ins, string opcodestr, string argstr>
101101
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
102102
bits<5> vs2;
103103
bits<5> vs1;
@@ -116,7 +116,7 @@ class RVInstMatmulF<dag outs, dag ins, string opcodestr, string argstr>
116116
}
117117

118118
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
119-
class RVInstMatmulF8<bit a, bit b, dag outs, dag ins,
119+
class SFInstMatmulF8<bit a, bit b, dag outs, dag ins,
120120
string opcodestr, string argstr>
121121
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
122122
bits<5> vs2;
@@ -147,7 +147,7 @@ defvar F8Encodes = [F8Encode<0b0, "e5m2">,
147147
F8Encode<0b1, "e4m3">];
148148

149149
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
150-
class RVInstMatmulI8<bit funct6_1, bit a, bit b, dag outs, dag ins,
150+
class SFInstMatmulI8<bit funct6_1, bit a, bit b, dag outs, dag ins,
151151
string opcodestr, string argstr>
152152
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
153153
bits<5> vs2;
@@ -178,7 +178,7 @@ defvar I8Encodes = [I8Encode<0, "u">,
178178
I8Encode<1, "s">];
179179

180180
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
181-
class RVInstSetZero<dag outs, dag ins, string opcodestr, string argstr>
181+
class SFInstSetZero<dag outs, dag ins, string opcodestr, string argstr>
182182
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
183183
bits<5> vs2;
184184
bits<5> vs1;
@@ -197,7 +197,7 @@ class RVInstSetZero<dag outs, dag ins, string opcodestr, string argstr>
197197
}
198198

199199
let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
200-
class RVInstVtDiscard<string opcodestr>
200+
class SFInstVtDiscard<string opcodestr>
201201
: RVInst<(outs), (ins), opcodestr, "", [], InstFormatR> {
202202
let Inst{31-26} = 0b010000;
203203
let Inst{25} = 1;
@@ -212,52 +212,50 @@ let Predicates = [HasVendorXSfmmbase] in
212212
def : InstAlias<"sf.vsettnt $rd, $rs1, $vtypei",
213213
(VSETVLI GPR:$rd, GPR:$rs1, XSfmmVTypeOp:$vtypei)>;
214214

215-
let DecoderNamespace = "XSfmm" in {
215+
let DecoderNamespace = "XSfvector" in {
216216

217217
let Predicates = [HasVendorXSfmmbase] in {
218-
def SF_VSETTN : RVInstSetSingle<(outs GPR:$rd), (ins GPR:$rs1), 0b00000,
218+
def SF_VSETTN : SFInstSetSingle<(outs GPR:$rd), (ins GPR:$rs1), 0b00000,
219219
"sf.vsettn", "$rd, $rs1">;
220-
def SF_VSETTM : RVInstSetSingle<(outs GPR:$rd), (ins GPR:$rs1), 0b00001,
220+
def SF_VSETTM : SFInstSetSingle<(outs GPR:$rd), (ins GPR:$rs1), 0b00001,
221221
"sf.vsettm", "$rd, $rs1">;
222-
def SF_VSETTK : RVInstSetSingle<(outs GPR:$rd), (ins GPR:$rs1), 0b00010,
222+
def SF_VSETTK : SFInstSetSingle<(outs GPR:$rd), (ins GPR:$rs1), 0b00010,
223223
"sf.vsettk", "$rd, $rs1">;
224-
def SF_VTDISCARD : RVInstVtDiscard<"sf.vtdiscard">;
224+
def SF_VTDISCARD : SFInstVtDiscard<"sf.vtdiscard">;
225225

226-
def SF_VTMV_V_T : RVInstTileMoveOp<0b010000, (outs VR:$vd), (ins GPR:$rs1),
226+
def SF_VTMV_V_T : SFInstTileMoveOp<0b010000, (outs VR:$vd), (ins GPR:$rs1),
227227
"sf.vtmv.v.t", "$vd, $rs1"> {
228228
let rs2 = 0b11111;
229229
}
230-
def SF_VTMV_T_V : RVInstTileMoveOp<0b010111, (outs), (ins GPR:$rs1, VR:$rs2),
230+
def SF_VTMV_T_V : SFInstTileMoveOp<0b010111, (outs), (ins GPR:$rs1, VR:$rs2),
231231
"sf.vtmv.t.v", "$rs1, $rs2"> {
232232
let vd = 0b00000;
233233
}
234234

235-
def SF_VTZERO_T : RVInstSetZero<(outs), (ins TR:$rd), "sf.vtzero.t", "$rd">;
236-
} // Predicates = [HasVendorXSfmmbase]
235+
def SF_VTZERO_T : SFInstSetZero<(outs), (ins TR:$rd), "sf.vtzero.t", "$rd">;
237236

238-
let Predicates = [HasVendorXSfmmbase] in {
239-
def SF_VLTE8 : RVInstTileLoad<0b000, "sf.vlte8">;
240-
def SF_VLTE16 : RVInstTileLoad<0b001, "sf.vlte16">;
241-
def SF_VLTE32 : RVInstTileLoad<0b010, "sf.vlte32">;
242-
def SF_VLTE64 : RVInstTileLoad<0b011, "sf.vlte64">;
243-
244-
def SF_VSTE8 : RVInstTileStore<0b000, "sf.vste8">;
245-
def SF_VSTE16 : RVInstTileStore<0b001, "sf.vste16">;
246-
def SF_VSTE32 : RVInstTileStore<0b010, "sf.vste32">;
247-
def SF_VSTE64 : RVInstTileStore<0b011, "sf.vste64">;
237+
def SF_VLTE8 : SFInstTileLoad<0b000, "sf.vlte8">;
238+
def SF_VLTE16 : SFInstTileLoad<0b001, "sf.vlte16">;
239+
def SF_VLTE32 : SFInstTileLoad<0b010, "sf.vlte32">;
240+
def SF_VLTE64 : SFInstTileLoad<0b011, "sf.vlte64">;
241+
242+
def SF_VSTE8 : SFInstTileStore<0b000, "sf.vste8">;
243+
def SF_VSTE16 : SFInstTileStore<0b001, "sf.vste16">;
244+
def SF_VSTE32 : SFInstTileStore<0b010, "sf.vste32">;
245+
def SF_VSTE64 : SFInstTileStore<0b011, "sf.vste64">;
248246
} // Predicates = [HasVendorXSfmmbase]
249247

250248
let Predicates = [HasVendorXSfmm32a16fOrXSfmm32a32fOrXSfmm64a64f] in {
251249
let Uses = [FRM], mayRaiseFPException = true in
252-
def SF_MM_F_F : RVInstMatmulF<(outs), (ins TRM2:$rd, VR:$vs2, VR:$vs1),
250+
def SF_MM_F_F : SFInstMatmulF<(outs), (ins TRM2:$rd, VR:$vs2, VR:$vs1),
253251
"sf.mm.f.f", "$rd, $vs2, $vs1">;
254252
} // Predicates = [HasVendorXSfmm32a16fOrXSfmm64a32fOrXSfmm64a64f]
255253

256254
let Predicates = [HasVendorXSfmm32a8i] in {
257255
foreach a = I8Encodes in
258256
foreach b = I8Encodes in
259257
def SF_MM_#!toupper(a.Name)#_#!toupper(b.Name)
260-
: RVInstMatmulI8<0, a.Encoding, b.Encoding,
258+
: SFInstMatmulI8<0, a.Encoding, b.Encoding,
261259
(outs), (ins TRM4:$rd, VR:$vs2, VR:$vs1),
262260
"sf.mm."#a.Name#"."#b.Name, "$rd, $vs2, $vs1">;
263261
} // Predicates = [HasVendorXSfmm32a8i]
@@ -267,10 +265,10 @@ let Uses = [FRM], mayRaiseFPException = true in {
267265
foreach a = F8Encodes in
268266
foreach b = F8Encodes in
269267
def SF_MM_#!toupper(a.Name)#_#!toupper(b.Name)
270-
: RVInstMatmulF8<a.Encoding, b.Encoding,
268+
: SFInstMatmulF8<a.Encoding, b.Encoding,
271269
(outs), (ins TRM4:$rd, VR:$vs2, VR:$vs1),
272270
"sf.mm."#a.Name#"."#b.Name, "$rd, $vs2, $vs1">;
273271
}
274272
} // Predicates = [HasVendorXSfmm32a8f]
275273

276-
} // DecoderNamespace = "XSfmm"
274+
} // DecoderNamespace = "XSfvector"

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