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michaelmaitlandmichaelmaitland
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fixup! fix operand number and add special case when no vlop
1 parent ab12f92 commit 4656b45

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5 files changed

+35
-3
lines changed

5 files changed

+35
-3
lines changed

‎llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1071,6 +1071,14 @@ bool RISCVVLOptimizer::checkUsers(const MachineOperand *&CommonVL,
10711071
"Expect LMUL 1 register class for vector as scalar operands!");
10721072
LLVM_DEBUG(dbgs() << " Used this operand as a scalar operand\n");
10731073
const MCInstrDesc &Desc = UserMI.getDesc();
1074+
// VMV_X_S and VFMV_F_S do not have a VL opt which would cause an assert
1075+
// assert failure if we called getVLOpNum. Therefore, we will set the
1076+
// CommonVL in that case as 1, even if it could have been set to 0.
1077+
if (!RISCVII::hasVLOp(Desc.TSFlags) || !RISCVII::hasSEWOp(Desc.TSFlags)) {
1078+
CommonVL = &One;
1079+
continue;
1080+
}
1081+
10741082
unsigned VLOpNum = RISCVII::getVLOpNum(Desc);
10751083
const MachineOperand &VLOp = UserMI.getOperand(VLOpNum);
10761084
if (VLOp.isReg() || (VLOp.isImm() && VLOp.getImm() != 0)) {

‎llvm/test/CodeGen/RISCV/double_reduct.ll‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -133,8 +133,11 @@ define i32 @mul_i32(<4 x i32> %a, <4 x i32> %b) {
133133
; RV32-NEXT: vslidedown.vi v10, v9, 2
134134
; RV32-NEXT: vmul.vv v9, v9, v10
135135
; RV32-NEXT: vrgather.vi v10, v8, 1
136+
; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
136137
; RV32-NEXT: vmul.vv v8, v8, v10
138+
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
137139
; RV32-NEXT: vrgather.vi v10, v9, 1
140+
; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
138141
; RV32-NEXT: vmul.vv v9, v9, v10
139142
; RV32-NEXT: vmv.x.s a0, v8
140143
; RV32-NEXT: vmv.x.s a1, v9
@@ -149,8 +152,11 @@ define i32 @mul_i32(<4 x i32> %a, <4 x i32> %b) {
149152
; RV64-NEXT: vslidedown.vi v10, v9, 2
150153
; RV64-NEXT: vmul.vv v9, v9, v10
151154
; RV64-NEXT: vrgather.vi v10, v8, 1
155+
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
152156
; RV64-NEXT: vmul.vv v8, v8, v10
157+
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
153158
; RV64-NEXT: vrgather.vi v10, v9, 1
159+
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
154160
; RV64-NEXT: vmul.vv v9, v9, v10
155161
; RV64-NEXT: vmv.x.s a0, v8
156162
; RV64-NEXT: vmv.x.s a1, v9

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1456,6 +1456,7 @@ define signext i8 @vpreduce_mul_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i3
14561456
; RV32-NEXT: vmv.v.i v9, 1
14571457
; RV32-NEXT: vmerge.vvm v8, v9, v8, v0
14581458
; RV32-NEXT: vrgather.vi v9, v8, 1
1459+
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
14591460
; RV32-NEXT: vmul.vv v8, v8, v9
14601461
; RV32-NEXT: vmv.x.s a0, v8
14611462
; RV32-NEXT: mv a1, a2
@@ -1483,6 +1484,7 @@ define signext i8 @vpreduce_mul_v2i8(i8 signext %s, <2 x i8> %v, <2 x i1> %m, i3
14831484
; RV64-NEXT: vmv.v.i v9, 1
14841485
; RV64-NEXT: vmerge.vvm v8, v9, v8, v0
14851486
; RV64-NEXT: vrgather.vi v9, v8, 1
1487+
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
14861488
; RV64-NEXT: vmul.vv v8, v8, v9
14871489
; RV64-NEXT: vmv.x.s a0, v8
14881490
; RV64-NEXT: mv a1, a2
@@ -1518,6 +1520,7 @@ define signext i8 @vpreduce_mul_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i3
15181520
; RV32-NEXT: vslidedown.vi v9, v8, 2
15191521
; RV32-NEXT: vmul.vv v8, v8, v9
15201522
; RV32-NEXT: vrgather.vi v9, v8, 1
1523+
; RV32-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
15211524
; RV32-NEXT: vmul.vv v8, v8, v9
15221525
; RV32-NEXT: vmv.x.s a0, v8
15231526
; RV32-NEXT: mv a1, a2
@@ -1547,6 +1550,7 @@ define signext i8 @vpreduce_mul_v4i8(i8 signext %s, <4 x i8> %v, <4 x i1> %m, i3
15471550
; RV64-NEXT: vslidedown.vi v9, v8, 2
15481551
; RV64-NEXT: vmul.vv v8, v8, v9
15491552
; RV64-NEXT: vrgather.vi v9, v8, 1
1553+
; RV64-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
15501554
; RV64-NEXT: vmul.vv v8, v8, v9
15511555
; RV64-NEXT: vmv.x.s a0, v8
15521556
; RV64-NEXT: mv a1, a2
@@ -1584,6 +1588,7 @@ define signext i8 @vpreduce_mul_v8i8(i8 signext %s, <8 x i8> %v, <8 x i1> %m, i3
15841588
; RV32-NEXT: vslidedown.vi v9, v8, 2
15851589
; RV32-NEXT: vmul.vv v8, v8, v9
15861590
; RV32-NEXT: vrgather.vi v9, v8, 1
1591+
; RV32-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
15871592
; RV32-NEXT: vmul.vv v8, v8, v9
15881593
; RV32-NEXT: vmv.x.s a0, v8
15891594
; RV32-NEXT: mv a1, a2
@@ -1615,6 +1620,7 @@ define signext i8 @vpreduce_mul_v8i8(i8 signext %s, <8 x i8> %v, <8 x i1> %m, i3
16151620
; RV64-NEXT: vslidedown.vi v9, v8, 2
16161621
; RV64-NEXT: vmul.vv v8, v8, v9
16171622
; RV64-NEXT: vrgather.vi v9, v8, 1
1623+
; RV64-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
16181624
; RV64-NEXT: vmul.vv v8, v8, v9
16191625
; RV64-NEXT: vmv.x.s a0, v8
16201626
; RV64-NEXT: mv a1, a2
@@ -1654,6 +1660,7 @@ define signext i8 @vpreduce_mul_v16i8(i8 signext %s, <16 x i8> %v, <16 x i1> %m,
16541660
; RV32-NEXT: vslidedown.vi v9, v8, 2
16551661
; RV32-NEXT: vmul.vv v8, v8, v9
16561662
; RV32-NEXT: vrgather.vi v9, v8, 1
1663+
; RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma
16571664
; RV32-NEXT: vmul.vv v8, v8, v9
16581665
; RV32-NEXT: vmv.x.s a0, v8
16591666
; RV32-NEXT: mv a1, a2
@@ -1687,6 +1694,7 @@ define signext i8 @vpreduce_mul_v16i8(i8 signext %s, <16 x i8> %v, <16 x i1> %m,
16871694
; RV64-NEXT: vslidedown.vi v9, v8, 2
16881695
; RV64-NEXT: vmul.vv v8, v8, v9
16891696
; RV64-NEXT: vrgather.vi v9, v8, 1
1697+
; RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma
16901698
; RV64-NEXT: vmul.vv v8, v8, v9
16911699
; RV64-NEXT: vmv.x.s a0, v8
16921700
; RV64-NEXT: mv a1, a2

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll‎

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5935,6 +5935,7 @@ define i8 @vreduce_mul_v2i8(ptr %x) {
59355935
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
59365936
; CHECK-NEXT: vle8.v v8, (a0)
59375937
; CHECK-NEXT: lbu a0, 1(a0)
5938+
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
59385939
; CHECK-NEXT: vmul.vx v8, v8, a0
59395940
; CHECK-NEXT: vmv.x.s a0, v8
59405941
; CHECK-NEXT: ret
@@ -5977,6 +5978,7 @@ define i8 @vreduce_mul_v4i8(ptr %x) {
59775978
; CHECK-NEXT: vslidedown.vi v9, v8, 2
59785979
; CHECK-NEXT: vmul.vv v8, v8, v9
59795980
; CHECK-NEXT: vrgather.vi v9, v8, 1
5981+
; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
59805982
; CHECK-NEXT: vmul.vv v8, v8, v9
59815983
; CHECK-NEXT: vmv.x.s a0, v8
59825984
; CHECK-NEXT: ret
@@ -5997,6 +5999,7 @@ define i8 @vreduce_mul_v8i8(ptr %x) {
59975999
; CHECK-NEXT: vslidedown.vi v9, v8, 2
59986000
; CHECK-NEXT: vmul.vv v8, v8, v9
59996001
; CHECK-NEXT: vrgather.vi v9, v8, 1
6002+
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
60006003
; CHECK-NEXT: vmul.vv v8, v8, v9
60016004
; CHECK-NEXT: vmv.x.s a0, v8
60026005
; CHECK-NEXT: ret
@@ -6019,6 +6022,7 @@ define i8 @vreduce_mul_v16i8(ptr %x) {
60196022
; CHECK-NEXT: vslidedown.vi v9, v8, 2
60206023
; CHECK-NEXT: vmul.vv v8, v8, v9
60216024
; CHECK-NEXT: vrgather.vi v9, v8, 1
6025+
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
60226026
; CHECK-NEXT: vmul.vv v8, v8, v9
60236027
; CHECK-NEXT: vmv.x.s a0, v8
60246028
; CHECK-NEXT: ret
@@ -6167,6 +6171,7 @@ define i16 @vreduce_mul_v2i16(ptr %x) {
61676171
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
61686172
; CHECK-NEXT: vle16.v v8, (a0)
61696173
; CHECK-NEXT: lh a0, 2(a0)
6174+
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
61706175
; CHECK-NEXT: vmul.vx v8, v8, a0
61716176
; CHECK-NEXT: vmv.x.s a0, v8
61726177
; CHECK-NEXT: ret
@@ -6185,6 +6190,7 @@ define i16 @vreduce_mul_v4i16(ptr %x) {
61856190
; CHECK-NEXT: vslidedown.vi v9, v8, 2
61866191
; CHECK-NEXT: vmul.vv v8, v8, v9
61876192
; CHECK-NEXT: vrgather.vi v9, v8, 1
6193+
; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
61886194
; CHECK-NEXT: vmul.vv v8, v8, v9
61896195
; CHECK-NEXT: vmv.x.s a0, v8
61906196
; CHECK-NEXT: ret
@@ -6205,6 +6211,7 @@ define i16 @vreduce_mul_v8i16(ptr %x) {
62056211
; CHECK-NEXT: vslidedown.vi v9, v8, 2
62066212
; CHECK-NEXT: vmul.vv v8, v8, v9
62076213
; CHECK-NEXT: vrgather.vi v9, v8, 1
6214+
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
62086215
; CHECK-NEXT: vmul.vv v8, v8, v9
62096216
; CHECK-NEXT: vmv.x.s a0, v8
62106217
; CHECK-NEXT: ret
@@ -6341,6 +6348,7 @@ define i32 @vreduce_mul_v2i32(ptr %x) {
63416348
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
63426349
; CHECK-NEXT: vle32.v v8, (a0)
63436350
; CHECK-NEXT: lw a0, 4(a0)
6351+
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
63446352
; CHECK-NEXT: vmul.vx v8, v8, a0
63456353
; CHECK-NEXT: vmv.x.s a0, v8
63466354
; CHECK-NEXT: ret
@@ -6359,6 +6367,7 @@ define i32 @vreduce_mul_v4i32(ptr %x) {
63596367
; CHECK-NEXT: vslidedown.vi v9, v8, 2
63606368
; CHECK-NEXT: vmul.vv v8, v8, v9
63616369
; CHECK-NEXT: vrgather.vi v9, v8, 1
6370+
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
63626371
; CHECK-NEXT: vmul.vv v8, v8, v9
63636372
; CHECK-NEXT: vmv.x.s a0, v8
63646373
; CHECK-NEXT: ret
@@ -6496,9 +6505,9 @@ define i64 @vreduce_mul_v2i64(ptr %x) {
64966505
; RV32-NEXT: addi a0, a0, 8
64976506
; RV32-NEXT: vlse64.v v9, (a0), zero
64986507
; RV32-NEXT: li a1, 32
6508+
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
64996509
; RV32-NEXT: vmul.vv v8, v8, v9
65006510
; RV32-NEXT: vmv.x.s a0, v8
6501-
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
65026511
; RV32-NEXT: vsrl.vx v8, v8, a1
65036512
; RV32-NEXT: vmv.x.s a1, v8
65046513
; RV32-NEXT: ret
@@ -6508,6 +6517,7 @@ define i64 @vreduce_mul_v2i64(ptr %x) {
65086517
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
65096518
; RV64-NEXT: vle64.v v8, (a0)
65106519
; RV64-NEXT: ld a0, 8(a0)
6520+
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
65116521
; RV64-NEXT: vmul.vx v8, v8, a0
65126522
; RV64-NEXT: vmv.x.s a0, v8
65136523
; RV64-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/fold-scalar-load-crash.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ define i32 @test(i32 %size, ptr %add.ptr, i64 %const) {
2121
; RV32-NEXT: vsetivli zero, 1, e8, m1, tu, ma
2222
; RV32-NEXT: vmv1r.v v9, v8
2323
; RV32-NEXT: vmv.s.x v9, a0
24-
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
24+
; RV32-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
2525
; RV32-NEXT: vmseq.vi v9, v9, 0
2626
; RV32-NEXT: vmv.x.s a0, v9
2727
; RV32-NEXT: andi a3, a0, 255
@@ -48,7 +48,7 @@ define i32 @test(i32 %size, ptr %add.ptr, i64 %const) {
4848
; RV64-NEXT: vsetivli zero, 1, e8, m1, tu, ma
4949
; RV64-NEXT: vmv1r.v v9, v8
5050
; RV64-NEXT: vmv.s.x v9, a0
51-
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
51+
; RV64-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
5252
; RV64-NEXT: vmseq.vi v9, v9, 0
5353
; RV64-NEXT: vmv.x.s a0, v9
5454
; RV64-NEXT: andi a3, a0, 255

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