Remove symbol parsing support for gp-related instruction

Author: tclin914

llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV_nonstandard.def

@@ -29,11 +29,3 @@ ELF_RISCV_NONSTANDARD_RELOC(QUALCOMM, R_RISCV_QC_E_CALL_PLT, 195)
 
 // Andes Nonstandard Relocations
 ELF_RISCV_NONSTANDARD_RELOC(ANDES, R_RISCV_NDS_BRANCH_10,    241)
-ELF_RISCV_NONSTANDARD_RELOC(ANDES, R_RISCV_NDS_GPREL_18S0_I, 246)
-ELF_RISCV_NONSTANDARD_RELOC(ANDES, R_RISCV_NDS_GPREL_17S1_I, 247)
-ELF_RISCV_NONSTANDARD_RELOC(ANDES, R_RISCV_NDS_GPREL_17S2_I, 248)
-ELF_RISCV_NONSTANDARD_RELOC(ANDES, R_RISCV_NDS_GPREL_17S3_I, 249)
-ELF_RISCV_NONSTANDARD_RELOC(ANDES, R_RISCV_NDS_GPREL_18S0_S, 250)
-ELF_RISCV_NONSTANDARD_RELOC(ANDES, R_RISCV_NDS_GPREL_17S1_S, 251)
-ELF_RISCV_NONSTANDARD_RELOC(ANDES, R_RISCV_NDS_GPREL_17S2_S, 252)
-ELF_RISCV_NONSTANDARD_RELOC(ANDES, R_RISCV_NDS_GPREL_17S3_S, 253)

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

@@ -534,14 +534,14 @@ struct RISCVOperand final : public MCParsedAsmOperand {
   }
 
   // True if operand is a symbol with no modifiers, or a constant with no
-  // modifiers and isShiftedInt<N-K, K>(Op).
-  template <int N, int K> bool isBareSimmNLsbK() const {
+  // modifiers and isShiftedInt<N-1, 1>(Op).
+  template <int N> bool isBareSimmNLsb0() const {
     if (!isImm())
       return false;
 
     int64_t Imm;
     if (evaluateConstantImm(getImm(), Imm))
-      return isShiftedInt<N - K, K>(fixImmediateForRV32(Imm, isRV64Imm()));
+      return isShiftedInt<N - 1, 1>(fixImmediateForRV32(Imm, isRV64Imm()));
 
     RISCV::Specifier VK = RISCV::S_None;
     return RISCVAsmParser::classifySymbolRef(getImm(), VK) &&
@@ -947,6 +947,22 @@ struct RISCVOperand final : public MCParsedAsmOperand {
         [](int64_t Imm) { return Imm != INT64_MIN && isInt<5>(Imm - 1); });
   }
 
+  bool isSImm18() const {
+    return isSImmPred([](int64_t Imm) { return isInt<18>(Imm); });
+  }
+
+  bool isSImm18Lsb0() const {
+    return isSImmPred([](int64_t Imm) { return isShiftedInt<17, 1>(Imm); });
+  }
+
+  bool isSImm19Lsb00() const {
+    return isSImmPred([](int64_t Imm) { return isShiftedInt<17, 2>(Imm); });
+  }
+
+  bool isSImm20Lsb000() const {
+    return isSImmPred([](int64_t Imm) { return isShiftedInt<17, 3>(Imm); });
+  }
+
   bool isSImm32Lsb0() const {
     return isSImmPred([](int64_t Imm) { return isShiftedInt<31, 1>(Imm); });
   }
@@ -1603,18 +1619,18 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                       (1 << 4),
                                       "immediate must be in the range");
   }
-  case Match_InvalidBareSImm18:
+  case Match_InvalidSImm18:
     return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 17),
                                       (1 << 17) - 1);
-  case Match_InvalidBareSImm18Lsb0:
+  case Match_InvalidSImm18Lsb0:
     return generateImmOutOfRangeError(
         Operands, ErrorInfo, -(1 << 17), (1 << 17) - 2,
         "immediate must be a multiple of 2 bytes in the range");
-  case Match_InvalidBareSImm19Lsb00:
+  case Match_InvalidSImm19Lsb00:
     return generateImmOutOfRangeError(
         Operands, ErrorInfo, -(1 << 18), (1 << 18) - 4,
         "immediate must be a multiple of 4 bytes in the range");
-  case Match_InvalidBareSImm20Lsb000:
+  case Match_InvalidSImm20Lsb000:
     return generateImmOutOfRangeError(
         Operands, ErrorInfo, -(1 << 19), (1 << 19) - 8,
         "immediate must be a multiple of 8 bytes in the range");

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

@@ -57,20 +57,12 @@ enum {
   InstFormatQC_EJ = 25,
   InstFormatQC_ES = 26,
   InstFormatNDS_BRANCH_10 = 27,
-  InstFormatNDS_GPREL_18S0_I = 28,
-  InstFormatNDS_GPREL_17S1_I = 29,
-  InstFormatNDS_GPREL_17S2_I = 30,
-  InstFormatNDS_GPREL_17S3_I = 31,
-  InstFormatNDS_GPREL_18S0_S = 32,
-  InstFormatNDS_GPREL_17S1_S = 33,
-  InstFormatNDS_GPREL_17S2_S = 34,
-  InstFormatNDS_GPREL_17S3_S = 35,
-  InstFormatOther = 63,
-
-  InstFormatMask = 63,
+  InstFormatOther = 31,
+
+  InstFormatMask = 31,
   InstFormatShift = 0,
 
-  ConstraintShift = InstFormatShift + 6,
+  ConstraintShift = InstFormatShift + 5,
   VS2Constraint = 0b001 << ConstraintShift,
   VS1Constraint = 0b010 << ConstraintShift,
   VMConstraint = 0b100 << ConstraintShift,

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

@@ -649,22 +649,6 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
       RelaxCandidate = true;
     } else if (MIFrm == RISCVII::InstFormatNDS_BRANCH_10) {
       FixupKind = RISCV::fixup_riscv_nds_branch_10;
-    } else if (MIFrm == RISCVII::InstFormatNDS_GPREL_18S0_I) {
-      FixupKind = ELF::R_RISCV_NDS_GPREL_18S0_I;
-    } else if (MIFrm == RISCVII::InstFormatNDS_GPREL_17S1_I) {
-      FixupKind = ELF::R_RISCV_NDS_GPREL_17S1_I;
-    } else if (MIFrm == RISCVII::InstFormatNDS_GPREL_17S2_I) {
-      FixupKind = ELF::R_RISCV_NDS_GPREL_17S2_I;
-    } else if (MIFrm == RISCVII::InstFormatNDS_GPREL_17S3_I) {
-      FixupKind = ELF::R_RISCV_NDS_GPREL_17S3_I;
-    } else if (MIFrm == RISCVII::InstFormatNDS_GPREL_18S0_S) {
-      FixupKind = ELF::R_RISCV_NDS_GPREL_18S0_S;
-    } else if (MIFrm == RISCVII::InstFormatNDS_GPREL_17S1_S) {
-      FixupKind = ELF::R_RISCV_NDS_GPREL_17S1_S;
-    } else if (MIFrm == RISCVII::InstFormatNDS_GPREL_17S2_S) {
-      FixupKind = ELF::R_RISCV_NDS_GPREL_17S2_S;
-    } else if (MIFrm == RISCVII::InstFormatNDS_GPREL_17S3_S) {
-      FixupKind = ELF::R_RISCV_NDS_GPREL_17S3_S;
     }
   }
 

llvm/lib/Target/RISCV/RISCVInstrFormats.td

@@ -27,46 +27,38 @@
 // Format specifies the encoding used by the instruction. This is used by
 // RISCVMCCodeEmitter to determine which form of fixup to use. These
 // definitions must be kept in-sync with RISCVBaseInfo.h.
-class InstFormat<bits<6> val> {
-  bits<6> Value = val;
-}
-def InstFormatPseudo           : InstFormat<0>;
-def InstFormatR                : InstFormat<1>;
-def InstFormatR4               : InstFormat<2>;
-def InstFormatI                : InstFormat<3>;
-def InstFormatS                : InstFormat<4>;
-def InstFormatB                : InstFormat<5>;
-def InstFormatU                : InstFormat<6>;
-def InstFormatJ                : InstFormat<7>;
-def InstFormatCR               : InstFormat<8>;
-def InstFormatCI               : InstFormat<9>;
-def InstFormatCSS              : InstFormat<10>;
-def InstFormatCIW              : InstFormat<11>;
-def InstFormatCL               : InstFormat<12>;
-def InstFormatCS               : InstFormat<13>;
-def InstFormatCA               : InstFormat<14>;
-def InstFormatCB               : InstFormat<15>;
-def InstFormatCJ               : InstFormat<16>;
-def InstFormatCU               : InstFormat<17>;
-def InstFormatCLB              : InstFormat<18>;
-def InstFormatCLH              : InstFormat<19>;
-def InstFormatCSB              : InstFormat<20>;
-def InstFormatCSH              : InstFormat<21>;
-def InstFormatQC_EAI           : InstFormat<22>;
-def InstFormatQC_EI            : InstFormat<23>;
-def InstFormatQC_EB            : InstFormat<24>;
-def InstFormatQC_EJ            : InstFormat<25>;
-def InstFormatQC_ES            : InstFormat<26>;
-def InstFormatNDS_BRANCH_10    : InstFormat<27>;
-def InstFormatNDS_GPREL_18S0_I : InstFormat<28>;
-def InstFormatNDS_GPREL_17S1_I : InstFormat<29>;
-def InstFormatNDS_GPREL_17S2_I : InstFormat<30>;
-def InstFormatNDS_GPREL_17S3_I : InstFormat<31>;
-def InstFormatNDS_GPREL_18S0_S : InstFormat<32>;
-def InstFormatNDS_GPREL_17S1_S : InstFormat<33>;
-def InstFormatNDS_GPREL_17S2_S : InstFormat<34>;
-def InstFormatNDS_GPREL_17S3_S : InstFormat<35>;
-def InstFormatOther            : InstFormat<63>;
+class InstFormat<bits<5> val> {
+  bits<5> Value = val;
+}
+def InstFormatPseudo        : InstFormat<0>;
+def InstFormatR             : InstFormat<1>;
+def InstFormatR4            : InstFormat<2>;
+def InstFormatI             : InstFormat<3>;
+def InstFormatS             : InstFormat<4>;
+def InstFormatB             : InstFormat<5>;
+def InstFormatU             : InstFormat<6>;
+def InstFormatJ             : InstFormat<7>;
+def InstFormatCR            : InstFormat<8>;
+def InstFormatCI            : InstFormat<9>;
+def InstFormatCSS           : InstFormat<10>;
+def InstFormatCIW           : InstFormat<11>;
+def InstFormatCL            : InstFormat<12>;
+def InstFormatCS            : InstFormat<13>;
+def InstFormatCA            : InstFormat<14>;
+def InstFormatCB            : InstFormat<15>;
+def InstFormatCJ            : InstFormat<16>;
+def InstFormatCU            : InstFormat<17>;
+def InstFormatCLB           : InstFormat<18>;
+def InstFormatCLH           : InstFormat<19>;
+def InstFormatCSB           : InstFormat<20>;
+def InstFormatCSH           : InstFormat<21>;
+def InstFormatQC_EAI        : InstFormat<22>;
+def InstFormatQC_EI         : InstFormat<23>;
+def InstFormatQC_EB         : InstFormat<24>;
+def InstFormatQC_EJ         : InstFormat<25>;
+def InstFormatQC_ES         : InstFormat<26>;
+def InstFormatNDS_BRANCH_10 : InstFormat<27>;
+def InstFormatOther         : InstFormat<31>;
 
 
 class RISCVVConstraint<bits<3> val> {
@@ -201,50 +193,50 @@ class RVInstCommon<dag outs, dag ins, string opcodestr, string argstr,
   let AsmString = opcodestr # !if(!empty(argstr), "", "\t" # argstr);
   let Pattern = pattern;
 
-  let TSFlags{5-0} = format.Value;
+  let TSFlags{4-0} = format.Value;
 
   // Defaults
   RISCVVConstraint RVVConstraint = NoConstraint;
-  let TSFlags{8-6} = RVVConstraint.Value;
+  let TSFlags{7-5} = RVVConstraint.Value;
 
   bits<3> VLMul = 0;
-  let TSFlags{11-9} = VLMul;
+  let TSFlags{10-8} = VLMul;
 
   bit IsTiedPseudo = 0;
-  let TSFlags{12} = IsTiedPseudo;
+  let TSFlags{11} = IsTiedPseudo;
 
   bit HasSEWOp = 0;
-  let TSFlags{13} = HasSEWOp;
+  let TSFlags{12} = HasSEWOp;
 
   bit HasVLOp = 0;
-  let TSFlags{14} = HasVLOp;
+  let TSFlags{13} = HasVLOp;
 
   bit HasVecPolicyOp = 0;
-  let TSFlags{15} = HasVecPolicyOp;
+  let TSFlags{14} = HasVecPolicyOp;
 
   bit IsRVVWideningReduction = 0;
-  let TSFlags{16} = IsRVVWideningReduction;
+  let TSFlags{15} = IsRVVWideningReduction;
 
   bit UsesMaskPolicy = 0;
-  let TSFlags{17} = UsesMaskPolicy;
+  let TSFlags{16} = UsesMaskPolicy;
 
   // Indicates that the result can be considered sign extended from bit 31. Some
   // instructions with this flag aren't W instructions, but are either sign
   // extended from a smaller size, always outputs a small integer, or put zeros
   // in bits 63:31. Used by the SExtWRemoval pass.
   bit IsSignExtendingOpW = 0;
-  let TSFlags{18} = IsSignExtendingOpW;
+  let TSFlags{17} = IsSignExtendingOpW;
 
   bit HasRoundModeOp = 0;
-  let TSFlags{19} =  HasRoundModeOp;
+  let TSFlags{18} =  HasRoundModeOp;
 
   // This is only valid when HasRoundModeOp is set to 1. HasRoundModeOp is set
   // to 1 for vector fixed-point or floating-point intrinsics. This bit is
   // processed under pass 'RISCVInsertReadWriteCSR' pass to distinguish between
   // fixed-point / floating-point instructions and emit appropriate read/write
   // to the correct CSR.
   bit UsesVXRM = 0;
-  let TSFlags{20} =  UsesVXRM;
+  let TSFlags{19} =  UsesVXRM;
 
   // Indicates whether these instructions can partially overlap between source
   // registers and destination registers according to the vector spec.
@@ -253,19 +245,19 @@ class RVInstCommon<dag outs, dag ins, string opcodestr, string argstr,
   // 2 -> narrowing case
   // 3 -> widening case
   bits<2> TargetOverlapConstraintType = 0;
-  let TSFlags{22-21} = TargetOverlapConstraintType;
+  let TSFlags{21-20} = TargetOverlapConstraintType;
 
   // Most vector instructions are elementwise, but some may depend on the value
   // of VL (e.g. vslide1down.vx), and others may depend on the VL and mask
   // (e.g. vredsum.vs, viota.m). Mark these instructions so that peepholes avoid
   // changing their VL and/or mask.
   EltDeps ElementsDependOn = EltDepsNone;
-  let TSFlags{23} = ElementsDependOn.VL;
-  let TSFlags{24} = ElementsDependOn.Mask;
+  let TSFlags{22} = ElementsDependOn.VL;
+  let TSFlags{23} = ElementsDependOn.Mask;
 
   // Indicates the EEW of a vector instruction's destination operand.
   EEW DestEEW = EEWSEWx1;
-  let TSFlags{26-25} = DestEEW.Value;
+  let TSFlags{25-24} = DestEEW.Value;
 }
 
 class RVInst<dag outs, dag ins, string opcodestr, string argstr,

llvm/lib/Target/RISCV/RISCVInstrInfo.td

@@ -227,24 +227,9 @@ class UImmAsmOperand<int width, string suffix = "">
     : ImmAsmOperand<"U", width, suffix> {
 }
 
-class BareSImmNAsmOperand<int width>
-    : ImmAsmOperand<"BareS", width, ""> {
-  let PredicateMethod = "isBareSimmN<" # width # ">";
-}
-
 class BareSImmNLsb0AsmOperand<int width>
     : ImmAsmOperand<"BareS", width, "Lsb0"> {
-  let PredicateMethod = "isBareSimmNLsbK<" # width # ", 1>";
-}
-
-class BareSImmNLsb00AsmOperand<int width>
-    : ImmAsmOperand<"BareS", width, "Lsb00"> {
-  let PredicateMethod = "isBareSimmNLsbK<" # width # ", 2>";
-}
-
-class BareSImmNLsb000AsmOperand<int width>
-    : ImmAsmOperand<"BareS", width, "Lsb000"> {
-  let PredicateMethod = "isBareSimmNLsbK<" # width # ", 3>";
+  let PredicateMethod = "isBareSimmNLsb0<" # width # ">";
 }
 
 class RISCVOp<ValueType vt = XLenVT> : Operand<vt> {