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[RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (#128833)
This extension adds 10 instructions that provide hints to the interface simulation environment. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/ This patch adds assembler only support.
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‎clang/test/Driver/print-supported-extensions-riscv.c‎

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@@ -207,6 +207,7 @@
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// CHECK-NEXT: xqcilia 0.2 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
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// CHECK-NEXT: xqcilo 0.2 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
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// CHECK-NEXT: xqcilsm 0.2 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
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// CHECK-NEXT: xqcisim 0.2 'Xqcisim' (Qualcomm uC Simulation Hint Extension)
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// CHECK-NEXT: xqcisls 0.2 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
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// CHECK-NEXT: xrivosvisni 0.1 'XRivosVisni' (Rivos Vector Integer Small New)
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// CHECK-NEXT: xrivosvizip 0.1 'XRivosVizip' (Rivos Vector Register Zips)

‎llvm/docs/RISCVUsage.rst‎

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@@ -471,6 +471,9 @@ The current vendor extensions supported are:
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``experimental-Xqcilsm``
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LLVM implements `version 0.2 of the Qualcomm uC Load Store Multiple extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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``experimental-Xqcisim``
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LLVM implements `version 0.2 of the Qualcomm uC Simulation Hint extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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``experimental-Xqcisls``
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LLVM implements `version 0.2 of the Qualcomm uC Scaled Load Store extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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‎llvm/docs/ReleaseNotes.md‎

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@@ -126,6 +126,8 @@ Changes to the RISC-V Backend
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'Xqccmp' extension, which is a frame-pointer convention compatible version of
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Zcmp.
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* Added non-quadratic ``log-vrgather`` cost model for ``vrgather.vv`` instruction
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* Adds experimental assembler support for the Qualcomm uC 'Xqcisim` (Simulation Hint)
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extension.
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Changes to the WebAssembly Backend
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----------------------------------

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp‎

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@@ -653,7 +653,8 @@ static constexpr FeatureBitset XqciFeatureGroup = {
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RISCV::FeatureVendorXqcics, RISCV::FeatureVendorXqcicsr,
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RISCV::FeatureVendorXqciint, RISCV::FeatureVendorXqcili,
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RISCV::FeatureVendorXqcilia, RISCV::FeatureVendorXqcilo,
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RISCV::FeatureVendorXqcilsm, RISCV::FeatureVendorXqcisls,
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RISCV::FeatureVendorXqcilsm, RISCV::FeatureVendorXqcisim,
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RISCV::FeatureVendorXqcisls,
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};
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static constexpr FeatureBitset XSfVectorGroup = {

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

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@@ -1407,6 +1407,14 @@ def HasVendorXqccmp : Predicate<"Subtarget->hasVendorXqccmp()">,
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AssemblerPredicate<(all_of FeatureVendorXqccmp),
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"'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)">;
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def FeatureVendorXqcisim
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: RISCVExperimentalExtension<0, 2, "Qualcomm uC Simulation Hint Extension",
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[FeatureStdExtZca]>;
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def HasVendorXqcisim
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: Predicate<"Subtarget->hasVendorXqcisim()">,
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AssemblerPredicate<(all_of FeatureVendorXqcisim),
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"'Xqcisim' (Qualcomm uC Simulation Hint Extension)">;
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// Rivos Extension(s)
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def FeatureVendorXRivosVisni

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td‎

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@@ -336,6 +336,19 @@ class QCIInt_IMM<bits<1> funct1, string opcodestr>
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let Inst{24-20} = imm10{9-5};
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}
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class QCISim_NONE<bits<4> imm11_8, string opcodestr>
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: RVInstI<0b010, OPC_OP_IMM, (outs), (ins), opcodestr, ""> {
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let rs1 = 0;
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let rd = 0;
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let imm12 = {imm11_8, 0b00000000};
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}
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class QCISim_RS1<bits<4> imm11_8, string opcodestr>
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: RVInstI<0b010, OPC_OP_IMM, (outs), (ins GPR:$rs1), opcodestr, "$rs1"> {
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let rd = 0;
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let imm12 = {imm11_8, 0b00000000};
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}
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class QCIRVInstEIBase<bits<3> funct3, bits<2> funct2, dag outs,
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dag ins, string opcodestr, string argstr>
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: RVInst48<outs, ins, opcodestr, argstr, [], InstFormatOther> {
@@ -691,6 +704,41 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
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} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
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} // Predicates = [HasVendorXqcilia, IsRV32]
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let Predicates = [HasVendorXqcisim, IsRV32] in {
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let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
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def QC_PSYSCALLI : RVInstI<0b010, OPC_OP_IMM, (outs), (ins uimm10:$imm10),
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"qc.psyscalli", "$imm10"> {
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bits<10> imm10;
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let rs1 = 0;
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let rd = 0;
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let imm12 = {0b00, imm10};
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}
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def QC_PPUTCI : RVInstI<0b010, OPC_OP_IMM, (outs), (ins uimm8:$imm8),
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"qc.pputci", "$imm8"> {
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bits<8> imm8;
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let rs1 = 0;
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let rd = 0;
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let imm12 = {0b0100, imm8};
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}
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def QC_PCOREDUMP : QCISim_NONE<0b0110, "qc.pcoredump">;
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def QC_PPREGS : QCISim_NONE<0b0111, "qc.ppregs">;
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def QC_PPREG : QCISim_RS1<0b1000, "qc.ppreg">;
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def QC_PPUTC : QCISim_RS1<0b1001, "qc.pputc">;
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def QC_PPUTS : QCISim_RS1<0b1010, "qc.pputs">;
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def QC_PEXIT : QCISim_RS1<0b1011, "qc.pexit">;
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def QC_PSYSCALL : QCISim_RS1<0b1100, "qc.psyscall">;
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def QC_C_PTRACE : RVInst16CI<0b000, 0b10, (outs), (ins), "qc.c.ptrace", ""> {
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let rd = 0;
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let imm = 0;
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}
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} // mayLoad = 0, mayStore = 0, hasSideEffects = 1
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} // Predicates = [HasVendorXqcisim, IsRV32]
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} // DecoderNamespace = "Xqci"
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//===----------------------------------------------------------------------===//

‎llvm/lib/TargetParser/RISCVISAInfo.cpp‎

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@@ -746,7 +746,7 @@ Error RISCVISAInfo::checkDependency() {
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static constexpr StringLiteral XqciExts[] = {
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{"xqcia"}, {"xqciac"}, {"xqcibi"}, {"xqcibm"}, {"xqcicli"},
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{"xqcicm"}, {"xqcics"}, {"xqcicsr"}, {"xqciint"}, {"xqcili"},
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{"xqcilia"}, {"xqcilo"}, {"xqcilsm"}, {"xqcisls"}};
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{"xqcilia"}, {"xqcilo"}, {"xqcilsm"}, {"xqcisim"}, {"xqcisls"}};
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static constexpr StringLiteral ZcdOverlaps[] = {
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{"zcmt"}, {"zcmp"}, {"xqccmp"}, {"xqciac"}, {"xqcicm"}};
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‎llvm/test/CodeGen/RISCV/attributes.ll‎

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@@ -95,6 +95,7 @@
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilia %s -o - | FileCheck --check-prefix=RV32XQCILIA %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilo %s -o - | FileCheck --check-prefix=RV32XQCILO %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilsm %s -o - | FileCheck --check-prefix=RV32XQCILSM %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisim %s -o - | FileCheck --check-prefix=RV32XQCISIM %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisls %s -o - | FileCheck --check-prefix=RV32XQCISLS %s
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; RUN: llc -mtriple=riscv32 -mattr=+zaamo %s -o - | FileCheck --check-prefix=RV32ZAAMO %s
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; RUN: llc -mtriple=riscv32 -mattr=+zalrsc %s -o - | FileCheck --check-prefix=RV32ZALRSC %s
@@ -419,6 +420,7 @@
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; RV32XQCILIA: .attribute 5, "rv32i2p1_zca1p0_xqcilia0p2"
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; RV32XQCILO: .attribute 5, "rv32i2p1_zca1p0_xqcilo0p2"
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; RV32XQCILSM: .attribute 5, "rv32i2p1_xqcilsm0p2"
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; RV32XQCISIM: attribute 5, "rv32i2p1_zca1p0_xqcisim0p2"
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; RV32XQCISLS: .attribute 5, "rv32i2p1_xqcisls0p2"
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; RV32ZAAMO: .attribute 5, "rv32i2p1_zaamo1p0"
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; RV32ZALRSC: .attribute 5, "rv32i2p1_zalrsc1p0"

‎llvm/test/MC/RISCV/xqcisim-invalid.s‎

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# Xqcisim - Simulaton Hint Instructions
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# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcisim < %s 2>&1 \
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# RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s
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# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcisim < %s 2>&1 \
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# RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s
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# CHECK-PLUS: :[[@LINE+1]]:14: error: immediate must be an integer in the range [0, 1023]
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qc.psyscalli 1024
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# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
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qc.psyscalli
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# CHECK: :[[@LINE+1]]:18: error: invalid operand for instruction
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qc.psyscalli 23, x0
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# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisim' (Qualcomm uC Simulation Hint Extension)
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qc.psyscalli 1023
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# CHECK-PLUS: :[[@LINE+1]]:11: error: immediate must be an integer in the range [0, 255]
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qc.pputci 256
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# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
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qc.pputci
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# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction
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qc.pputci 200, x8
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# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisim' (Qualcomm uC Simulation Hint Extension)
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qc.pputci 255
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# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction
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qc.c.ptrace x0
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# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction
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qc.c.ptrace 1
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# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisim' (Qualcomm uC Simulation Hint Extension)
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qc.c.ptrace
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# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction
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qc.pcoredump 12
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# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction
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qc.pcoredump x4
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# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisim' (Qualcomm uC Simulation Hint Extension)
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qc.pcoredump
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# CHECK: :[[@LINE+1]]:11: error: invalid operand for instruction
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qc.ppregs x1
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# CHECK: :[[@LINE+1]]:11: error: invalid operand for instruction
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qc.ppregs 23
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# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisim' (Qualcomm uC Simulation Hint Extension)
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qc.ppregs
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# CHECK: :[[@LINE+1]]:15: error: invalid operand for instruction
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qc.ppreg x10, x2
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# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
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qc.ppreg
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# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction
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qc.ppreg 23
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# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisim' (Qualcomm uC Simulation Hint Extension)
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qc.ppreg a0
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# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction
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qc.pputc x7, x3
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# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
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qc.pputc
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# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction
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qc.pputc 34
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# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisim' (Qualcomm uC Simulation Hint Extension)
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qc.pputc t2
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# CHECK: :[[@LINE+1]]:15: error: invalid operand for instruction
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qc.pputs x15, x18
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# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
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qc.pputs
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# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction
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qc.pputs 45
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# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisim' (Qualcomm uC Simulation Hint Extension)
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qc.pputs a5
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# CHECK: :[[@LINE+1]]:15: error: invalid operand for instruction
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qc.pexit x26, x23
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# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
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qc.pexit
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# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction
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qc.pexit 78
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# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisim' (Qualcomm uC Simulation Hint Extension)
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qc.pexit s10
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# CHECK: :[[@LINE+1]]:18: error: invalid operand for instruction
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qc.psyscall x11, x5
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# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
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qc.psyscall
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# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction
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qc.psyscall 98
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# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcisim' (Qualcomm uC Simulation Hint Extension)
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qc.psyscall a1

‎llvm/test/MC/RISCV/xqcisim-valid.s‎

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# Xqcisim - Simulation Hint Instructions
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# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcisim -riscv-no-aliases -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisim < %s \
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# RUN: | llvm-objdump --mattr=+experimental-xqcisim -M no-aliases --no-print-imm-hex -d - \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
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# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcisim -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisim < %s \
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# RUN: | llvm-objdump --mattr=+experimental-xqcisim --no-print-imm-hex -d - \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
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# CHECK-INST: qc.psyscalli 1023
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# CHECK-ENC: encoding: [0x13,0x20,0xf0,0x3f]
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qc.psyscalli 1023
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# CHECK-INST: qc.pputci 255
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# CHECK-ENC: encoding: [0x13,0x20,0xf0,0x4f]
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qc.pputci 255
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# CHECK-INST: qc.c.ptrace
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# CHECK-ENC: encoding: [0x02,0x00]
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qc.c.ptrace
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# CHECK-INST: qc.pcoredump
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# CHECK-ENC: encoding: [0x13,0x20,0x00,0x60]
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qc.pcoredump
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# CHECK-INST: qc.ppregs
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# CHECK-ENC: encoding: [0x13,0x20,0x00,0x70]
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qc.ppregs
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# CHECK-INST: qc.ppreg a0
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# CHECK-ENC: encoding: [0x13,0x20,0x05,0x80]
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qc.ppreg x10
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# CHECK-INST: qc.pputc t2
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# CHECK-ENC: encoding: [0x13,0xa0,0x03,0x90]
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qc.pputc x7
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# CHECK-INST: qc.pputs a5
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# CHECK-ENC: encoding: [0x13,0xa0,0x07,0xa0]
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qc.pputs x15
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# CHECK-INST: qc.pexit s10
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# CHECK-ENC: encoding: [0x13,0x20,0x0d,0xb0]
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qc.pexit x26
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# CHECK-INST: qc.psyscall a1
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# CHECK-ENC: encoding: [0x13,0xa0,0x05,0xc0]
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qc.psyscall x11

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