Propoagte type from getTypeWidth and int64_t

Author: amd-eochoalo

mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp

@@ -2368,10 +2368,11 @@ struct AMDGPUMakeDmaDescriptorLowering
                     ConversionPatternRewriter &rewriter, Location loc,
                     Value sgpr0, ArrayRef<Value> consts) const {
     // Compute data_size.
-    int elementTypeWidthInBits = op.getElementTypeWidth();
-    assert(llvm::is_contained({8, 16, 32, 64}, elementTypeWidthInBits) &&
-           "expected type width to be 8, 16, 32, or 64.");
-    int dataSize = llvm::Log2_32(elementTypeWidthInBits / 8);
+    unsigned elementTypeWidthInBits = op.getElementTypeWidth();
+    assert(
+        llvm::is_contained<unsigned>({8, 16, 32, 64}, elementTypeWidthInBits) &&
+        "expected type width to be 8, 16, 32, or 64.");
+    int64_t dataSize = llvm::Log2_32(elementTypeWidthInBits / 8);
     return createI32Constant(rewriter, loc, dataSize << 16);
   }
 

mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp

@@ -759,8 +759,8 @@ LogicalResult MakeDmaDescriptorOp::verify() {
   if (rank != sharedStaticSizes.size())
     return emitOpError("tensor must have same rank as tile.");
 
-  int elementTypeWidth = getElementTypeWidth();
-  if (!llvm::is_contained({8, 16, 32, 64}, elementTypeWidth))
+  unsigned elementTypeWidth = getElementTypeWidth();
+  if (!llvm::is_contained<unsigned>({8, 16, 32, 64}, elementTypeWidth))
     return emitOpError(
                "element type width must be 1, 2, 4 or 8 bytes, but was ")
            << elementTypeWidth << " bits long";