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--Updated the test file
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‎llvm/docs/SPIRVUsage.rst‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -233,6 +233,18 @@ Below is a list of supported SPIR-V extensions, sorted alphabetically by their e
233233
- Adds support for 4-bit integer type, and allow this type to be used in cooperative matrices.
234234
* - ``SPV_KHR_float_controls2``
235235
- Adds ability to specify the floating-point environment in shaders. It can be used on whole modules and individual instructions.
236+
* - ``SPV_INTEL_arbitrary_precision_fixed_point``
237+
- Add instructions for fixed point arithmetic. The extension works without SPV_INTEL_arbitrary_precision_integers, but together they allow greater flexibility in representing arbitrary precision data types.
238+
239+
To enable multiple extensions, list them separated by comma. For example, to enable support for atomic operations on floating-point numbers and arbitrary precision integers, use:
240+
241+
``-spirv-ext=+SPV_EXT_shader_atomic_float_add,+SPV_INTEL_arbitrary_precision_integers``
242+
243+
To enable all extensions, use the following option:
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``-spirv-ext=all``
245+
246+
To enable all extensions except specified, specify ``all`` followed by a list of disallowed extensions. For example:
247+
``-spirv-ext=all,-SPV_INTEL_arbitrary_precision_integers``
236248

237249
SPIR-V representation in LLVM IR
238250
================================

‎llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp‎

Lines changed: 73 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2362,6 +2362,77 @@ static bool generateBindlessImageINTELInst(const SPIRV::IncomingCall *Call,
23622362
return buildBindlessImageINTELInst(Call, Opcode, MIRBuilder, GR);
23632363
}
23642364

2365+
static bool buildAPFixedPointInst(const SPIRV::IncomingCall *Call,
2366+
unsigned Opcode, MachineIRBuilder &MIRBuilder,
2367+
SPIRVGlobalRegistry *GR) {
2368+
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
2369+
SmallVector<uint32_t, 1> ImmArgs;
2370+
Register InputReg = Call->Arguments[0];
2371+
const Type *RetTy = GR->getTypeForSPIRVType(Call->ReturnType);
2372+
bool IsSRet = RetTy->isVoidTy();
2373+
2374+
if (IsSRet) {
2375+
const LLT ValTy = MRI->getType(InputReg);
2376+
Register ActualRetValReg = MRI->createGenericVirtualRegister(ValTy);
2377+
SPIRVType *InstructionType =
2378+
GR->getPointeeType(GR->getSPIRVTypeForVReg(InputReg));
2379+
InputReg = Call->Arguments[1];
2380+
auto InputType = GR->getTypeForSPIRVType(GR->getSPIRVTypeForVReg(InputReg));
2381+
Register PtrInputReg;
2382+
if (InputType->getTypeID() == llvm::Type::TypeID::TypedPointerTyID) {
2383+
LLT InputLLT = MRI->getType(InputReg);
2384+
PtrInputReg = MRI->createGenericVirtualRegister(InputLLT);
2385+
SPIRVType *PtrType =
2386+
GR->getPointeeType(GR->getSPIRVTypeForVReg(InputReg));
2387+
MachineMemOperand *MMO1 = MIRBuilder.getMF().getMachineMemOperand(
2388+
MachinePointerInfo(), MachineMemOperand::MOLoad,
2389+
InputLLT.getSizeInBytes(), Align(4));
2390+
MIRBuilder.buildLoad(PtrInputReg, InputReg, *MMO1);
2391+
MRI->setRegClass(PtrInputReg, &SPIRV::iIDRegClass);
2392+
GR->assignSPIRVTypeToVReg(PtrType, PtrInputReg, MIRBuilder.getMF());
2393+
}
2394+
2395+
for (unsigned index = 2; index < 7; index++) {
2396+
ImmArgs.push_back(getConstFromIntrinsic(Call->Arguments[index], MRI));
2397+
}
2398+
2399+
// Emit the instruction
2400+
auto MIB = MIRBuilder.buildInstr(Opcode)
2401+
.addDef(ActualRetValReg)
2402+
.addUse(GR->getSPIRVTypeID(InstructionType));
2403+
if (PtrInputReg)
2404+
MIB.addUse(PtrInputReg);
2405+
else
2406+
MIB.addUse(InputReg);
2407+
2408+
for (uint32_t Imm : ImmArgs)
2409+
MIB.addImm(Imm);
2410+
unsigned Size = ValTy.getSizeInBytes();
2411+
// Store result to the pointer passed in Arg[0]
2412+
MachineMemOperand *MMO = MIRBuilder.getMF().getMachineMemOperand(
2413+
MachinePointerInfo(), MachineMemOperand::MOStore, Size, Align(4));
2414+
MRI->setRegClass(ActualRetValReg, &SPIRV::pIDRegClass);
2415+
MIRBuilder.buildStore(ActualRetValReg, Call->Arguments[0], *MMO);
2416+
return true;
2417+
} else {
2418+
for (unsigned index = 1; index < 6; index++)
2419+
ImmArgs.push_back(getConstFromIntrinsic(Call->Arguments[index], MRI));
2420+
2421+
return buildOpFromWrapper(MIRBuilder, Opcode, Call,
2422+
GR->getSPIRVTypeID(Call->ReturnType), ImmArgs);
2423+
}
2424+
}
2425+
2426+
static bool generateAPFixedPointInst(const SPIRV::IncomingCall *Call,
2427+
MachineIRBuilder &MIRBuilder,
2428+
SPIRVGlobalRegistry *GR) {
2429+
const SPIRV::DemangledBuiltin *Builtin = Call->Builtin;
2430+
unsigned Opcode =
2431+
SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode;
2432+
2433+
return buildAPFixedPointInst(Call, Opcode, MIRBuilder, GR);
2434+
}
2435+
23652436
static bool
23662437
generateTernaryBitwiseFunctionINTELInst(const SPIRV::IncomingCall *Call,
23672438
MachineIRBuilder &MIRBuilder,
@@ -2993,6 +3064,8 @@ std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
29933064
return generateExtendedBitOpsInst(Call.get(), MIRBuilder, GR);
29943065
case SPIRV::BindlessINTEL:
29953066
return generateBindlessImageINTELInst(Call.get(), MIRBuilder, GR);
3067+
case SPIRV::ArbitraryPrecisionFixedPoint:
3068+
return generateAPFixedPointInst(Call.get(), MIRBuilder, GR);
29963069
case SPIRV::TernaryBitwiseINTEL:
29973070
return generateTernaryBitwiseFunctionINTELInst(Call.get(), MIRBuilder, GR);
29983071
case SPIRV::Block2DLoadStore:

‎llvm/lib/Target/SPIRV/SPIRVBuiltins.td‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -70,6 +70,7 @@ def BindlessINTEL : BuiltinGroup;
7070
def TernaryBitwiseINTEL : BuiltinGroup;
7171
def Block2DLoadStore : BuiltinGroup;
7272
def Pipe : BuiltinGroup;
73+
def ArbitraryPrecisionFixedPoint : BuiltinGroup;
7374

7475
//===----------------------------------------------------------------------===//
7576
// Class defining a demangled builtin record. The information in the record
@@ -1170,6 +1171,19 @@ defm : DemangledNativeBuiltin<"clock_read_hilo_device", OpenCL_std, KernelClock,
11701171
defm : DemangledNativeBuiltin<"clock_read_hilo_work_group", OpenCL_std, KernelClock, 0, 0, OpReadClockKHR>;
11711172
defm : DemangledNativeBuiltin<"clock_read_hilo_sub_group", OpenCL_std, KernelClock, 0, 0, OpReadClockKHR>;
11721173

1174+
//SPV_INTEL_arbitrary_precision_fixed_point
1175+
defm : DemangledNativeBuiltin<"__spirv_FixedSqrtINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSqrtINTEL>;
1176+
defm : DemangledNativeBuiltin<"__spirv_FixedRecipINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedRecipINTEL>;
1177+
defm : DemangledNativeBuiltin<"__spirv_FixedRsqrtINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedRsqrtINTEL>;
1178+
defm : DemangledNativeBuiltin<"__spirv_FixedSinINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinINTEL>;
1179+
defm : DemangledNativeBuiltin<"__spirv_FixedCosINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedCosINTEL>;
1180+
defm : DemangledNativeBuiltin<"__spirv_FixedSinCosINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinCosINTEL>;
1181+
defm : DemangledNativeBuiltin<"__spirv_FixedSinPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinPiINTEL>;
1182+
defm : DemangledNativeBuiltin<"__spirv_FixedCosPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedCosPiINTEL>;
1183+
defm : DemangledNativeBuiltin<"__spirv_FixedSinCosPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinCosPiINTEL>;
1184+
defm : DemangledNativeBuiltin<"__spirv_FixedLogINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedLogINTEL>;
1185+
defm : DemangledNativeBuiltin<"__spirv_FixedExpINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedExpINTEL>;
1186+
11731187
//===----------------------------------------------------------------------===//
11741188
// Class defining an atomic instruction on floating-point numbers.
11751189
//

‎llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -151,7 +151,11 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
151151
{"SPV_KHR_bfloat16", SPIRV::Extension::Extension::SPV_KHR_bfloat16},
152152
{"SPV_EXT_relaxed_printf_string_address_space",
153153
SPIRV::Extension::Extension::
154-
SPV_EXT_relaxed_printf_string_address_space}};
154+
SPV_EXT_relaxed_printf_string_address_space},
155+
{"SPV_INTEL_int4", SPIRV::Extension::Extension::SPV_INTEL_int4},
156+
{"SPV_INTEL_arbitrary_precision_fixed_point",
157+
SPIRV::Extension::Extension::
158+
SPV_INTEL_arbitrary_precision_fixed_point}};
155159

156160
bool SPIRVExtensionsParser::parse(cl::Option &O, StringRef ArgName,
157161
StringRef ArgValue,

‎llvm/lib/Target/SPIRV/SPIRVInstrInfo.td‎

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -987,3 +987,29 @@ def OpSubgroup2DBlockPrefetchINTEL: Op<6234, (outs), (ins ID:$element_size, ID:$
987987
def OpSubgroup2DBlockStoreINTEL: Op<6235, (outs), (ins ID:$element_size, ID:$block_width, ID:$block_height,
988988
ID:$block_count, ID:$src_ptr, ID:$dst_base_ptr, ID:$memory_width, ID:$memory_height, ID:$memory_pitch, ID:$coord),
989989
"OpSubgroup2DBlockStoreINTEL $element_size $block_width $block_height $block_count $src_ptr $dst_base_ptr $memory_width $memory_height $memory_pitch $coord">;
990+
991+
992+
993+
//SPV_INTEL_arbitrary_precision_fixed_point
994+
def OpFixedSqrtINTEL: Op<5923, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
995+
"$res = OpFixedSqrtINTEL $result_type $input $sign $l $rl $q $o">;
996+
def OpFixedRecipINTEL: Op<5924, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
997+
"$res = OpFixedRecipINTEL $result_type $input $sign $l $rl $q $o">;
998+
def OpFixedRsqrtINTEL: Op<5925, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
999+
"$res = OpFixedRsqrtINTEL $result_type $input $sign $l $rl $q $o">;
1000+
def OpFixedSinINTEL: Op<5926, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1001+
"$res = OpFixedSinINTEL $result_type $input $sign $l $rl $q $o">;
1002+
def OpFixedCosINTEL: Op<5927, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1003+
"$res = OpFixedCosINTEL $result_type $input $sign $l $rl $q $o">;
1004+
def OpFixedSinCosINTEL: Op<5928, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1005+
"$res = OpFixedSinCosINTEL $result_type $input $sign $l $rl $q $o">;
1006+
def OpFixedSinPiINTEL: Op<5929, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1007+
"$res = OpFixedSinPiINTEL $result_type $input $sign $l $rl $q $o">;
1008+
def OpFixedCosPiINTEL: Op<5930, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1009+
"$res = OpFixedCosPiINTEL $result_type $input $sign $l $rl $q $o">;
1010+
def OpFixedSinCosPiINTEL: Op<5931, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1011+
"$res = OpFixedSinCosPiINTEL $result_type $input $sign $l $rl $q $o">;
1012+
def OpFixedLogINTEL: Op<5932, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1013+
"$res = OpFixedLogINTEL $result_type $input $sign $l $rl $q $o">;
1014+
def OpFixedExpINTEL: Op<5933, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
1015+
"$res = OpFixedExpINTEL $result_type $input $sign $l $rl $q $o">;

‎llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1587,6 +1587,27 @@ void addInstrRequirements(const MachineInstr &MI,
15871587
Reqs.addCapability(SPIRV::Capability::GroupNonUniformRotateKHR);
15881588
Reqs.addCapability(SPIRV::Capability::GroupNonUniform);
15891589
break;
1590+
case SPIRV::OpFixedCosINTEL:
1591+
case SPIRV::OpFixedSinINTEL:
1592+
case SPIRV::OpFixedCosPiINTEL:
1593+
case SPIRV::OpFixedSinPiINTEL:
1594+
case SPIRV::OpFixedExpINTEL:
1595+
case SPIRV::OpFixedLogINTEL:
1596+
case SPIRV::OpFixedRecipINTEL:
1597+
case SPIRV::OpFixedSqrtINTEL:
1598+
case SPIRV::OpFixedSinCosINTEL:
1599+
case SPIRV::OpFixedSinCosPiINTEL:
1600+
case SPIRV::OpFixedRsqrtINTEL:
1601+
if (!ST.canUseExtension(
1602+
SPIRV::Extension::SPV_INTEL_arbitrary_precision_fixed_point))
1603+
report_fatal_error("This instruction requires the "
1604+
"following SPIR-V extension: "
1605+
"SPV_INTEL_arbitrary_precision_fixed_point",
1606+
false);
1607+
Reqs.addExtension(
1608+
SPIRV::Extension::SPV_INTEL_arbitrary_precision_fixed_point);
1609+
Reqs.addCapability(SPIRV::Capability::ArbitraryPrecisionFixedPointINTEL);
1610+
break;
15901611
case SPIRV::OpGroupIMulKHR:
15911612
case SPIRV::OpGroupFMulKHR:
15921613
case SPIRV::OpGroupBitwiseAndKHR:

‎llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -385,6 +385,7 @@ defm SPV_INTEL_int4 : ExtensionOperand<123, [EnvOpenCL]>;
385385
defm SPV_KHR_float_controls2 : ExtensionOperand<124, [EnvVulkan, EnvOpenCL]>;
386386
defm SPV_INTEL_tensor_float32_conversion : ExtensionOperand<125, [EnvOpenCL]>;
387387
defm SPV_KHR_bfloat16 : ExtensionOperand<126, [EnvVulkan, EnvOpenCL]>;
388+
defm SPV_INTEL_arbitrary_precision_fixed_point : ExtensionOperand<127, [EnvOpenCL]>;
388389

389390
//===----------------------------------------------------------------------===//
390391
// Multiclass used to define Capabilities enum values and at the same time
@@ -597,9 +598,13 @@ defm Subgroup2DBlockTransposeINTEL : CapabilityOperand<6230, 0, 0, [SPV_INTEL_2d
597598
defm Int4TypeINTEL : CapabilityOperand<5112, 0, 0, [SPV_INTEL_int4], []>;
598599
defm Int4CooperativeMatrixINTEL : CapabilityOperand<5114, 0, 0, [SPV_INTEL_int4], [Int4TypeINTEL, CooperativeMatrixKHR]>;
599600
defm TensorFloat32RoundingINTEL : CapabilityOperand<6425, 0, 0, [SPV_INTEL_tensor_float32_conversion], []>;
601+
<<<<<<< HEAD
600602
defm BFloat16TypeKHR : CapabilityOperand<5116, 0, 0, [SPV_KHR_bfloat16], []>;
601603
defm BFloat16DotProductKHR : CapabilityOperand<5117, 0, 0, [SPV_KHR_bfloat16], [BFloat16TypeKHR]>;
602604
defm BFloat16CooperativeMatrixKHR : CapabilityOperand<5118, 0, 0, [SPV_KHR_bfloat16], [BFloat16TypeKHR, CooperativeMatrixKHR]>;
605+
=======
606+
defm ArbitraryPrecisionFixedPointINTEL : CapabilityOperand<5922, 0, 0, [SPV_INTEL_arbitrary_precision_fixed_point], []>;
607+
>>>>>>> 3bfee8723b1d (--Updated the test file)
603608

604609
//===----------------------------------------------------------------------===//
605610
// Multiclass used to define SourceLanguage enum values and at the same time

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