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[ARM] Port AArch64's CSel handling patterns to ARM
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14 files changed

+3417
-3217
lines changed

14 files changed

+3417
-3217
lines changed

‎llvm/lib/Target/ARM/ARMInstrThumb2.td‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5765,6 +5765,15 @@ let Predicates = [HasV8_1MMainline] in {
57655765
def : T2Pat<(ARMcmov (i32 0), (i32 -1), imm:$cc, CPSR),
57665766
(t2CSINV ZR, ZR, (inv_cond_XFORM imm:$cc))>;
57675767

5768+
def : T2Pat<(ARMcmov GPRwithZR:$tval, (i32 1), imm:$cc, CPSR),
5769+
(t2CSINC GPRwithZR:$tval, ZR, imm:$cc)>;
5770+
def : T2Pat<(ARMcmov (i32 1), GPRwithZR:$fval, imm:$cc, CPSR),
5771+
(t2CSINC GPRwithZR:$fval, ZR, (inv_cond_XFORM imm:$cc))>;
5772+
def : T2Pat<(ARMcmov GPRwithZR:$tval, (i32 -1), imm:$cc, CPSR),
5773+
(t2CSINV GPRwithZR:$tval, ZR, imm:$cc)>;
5774+
def : T2Pat<(ARMcmov (i32 -1), GPRwithZR:$fval, imm:$cc, CPSR),
5775+
(t2CSINV GPRwithZR:$fval, ZR, (inv_cond_XFORM imm:$cc))>;
5776+
57685777
multiclass ModifiedV8_1CSEL<Instruction Insn, dag modvalue> {
57695778
def : T2Pat<(ARMcmov modvalue, GPRwithZR:$tval, imm:$cc, CPSR),
57705779
(Insn GPRwithZR:$tval, GPRwithZR:$fval, imm:$cc)>;

‎llvm/test/CodeGen/ARM/fpclamptosat.ll‎

Lines changed: 66 additions & 66 deletions
Original file line numberDiff line numberDiff line change
@@ -1039,8 +1039,8 @@ define i64 @stest_f64i64(double %x) {
10391039
;
10401040
; FULL-LABEL: stest_f64i64:
10411041
; FULL: @ %bb.0: @ %entry
1042-
; FULL-NEXT: .save {r4, r5, r7, lr}
1043-
; FULL-NEXT: push {r4, r5, r7, lr}
1042+
; FULL-NEXT: .save {r4, lr}
1043+
; FULL-NEXT: push {r4, lr}
10441044
; FULL-NEXT: bl __fixdfti
10451045
; FULL-NEXT: subs.w lr, r0, #-1
10461046
; FULL-NEXT: mvn r12, #-2147483648
@@ -1049,20 +1049,20 @@ define i64 @stest_f64i64(double %x) {
10491049
; FULL-NEXT: sbcs lr, r3, #0
10501050
; FULL-NEXT: cset lr, lt
10511051
; FULL-NEXT: cmp.w lr, #0
1052-
; FULL-NEXT: csel r5, r3, lr, ne
1053-
; FULL-NEXT: mov.w r3, #-1
1054-
; FULL-NEXT: csel r0, r0, r3, ne
1052+
; FULL-NEXT: csinv r0, r0, zr, eq
10551053
; FULL-NEXT: csel r1, r1, r12, ne
1054+
; FULL-NEXT: csel r3, r3, lr, ne
10561055
; FULL-NEXT: csel r2, r2, lr, ne
10571056
; FULL-NEXT: rsbs r4, r0, #0
1058-
; FULL-NEXT: mov.w r12, #-2147483648
1059-
; FULL-NEXT: sbcs.w r4, r12, r1
1060-
; FULL-NEXT: sbcs.w r2, r3, r2
1061-
; FULL-NEXT: sbcs.w r2, r3, r5
1057+
; FULL-NEXT: mov.w lr, #-2147483648
1058+
; FULL-NEXT: sbcs.w r4, lr, r1
1059+
; FULL-NEXT: mov.w r12, #-1
1060+
; FULL-NEXT: sbcs.w r2, r12, r2
1061+
; FULL-NEXT: sbcs.w r2, r12, r3
10621062
; FULL-NEXT: it ge
10631063
; FULL-NEXT: movge r0, #0
1064-
; FULL-NEXT: csel r1, r1, r12, lt
1065-
; FULL-NEXT: pop {r4, r5, r7, pc}
1064+
; FULL-NEXT: csel r1, r1, lr, lt
1065+
; FULL-NEXT: pop {r4, pc}
10661066
entry:
10671067
%conv = fptosi double %x to i128
10681068
%0 = icmp slt i128 %conv, 9223372036854775807
@@ -1295,8 +1295,8 @@ define i64 @stest_f32i64(float %x) {
12951295
;
12961296
; FULL-LABEL: stest_f32i64:
12971297
; FULL: @ %bb.0: @ %entry
1298-
; FULL-NEXT: .save {r4, r5, r7, lr}
1299-
; FULL-NEXT: push {r4, r5, r7, lr}
1298+
; FULL-NEXT: .save {r4, lr}
1299+
; FULL-NEXT: push {r4, lr}
13001300
; FULL-NEXT: bl __fixsfti
13011301
; FULL-NEXT: subs.w lr, r0, #-1
13021302
; FULL-NEXT: mvn r12, #-2147483648
@@ -1305,20 +1305,20 @@ define i64 @stest_f32i64(float %x) {
13051305
; FULL-NEXT: sbcs lr, r3, #0
13061306
; FULL-NEXT: cset lr, lt
13071307
; FULL-NEXT: cmp.w lr, #0
1308-
; FULL-NEXT: csel r5, r3, lr, ne
1309-
; FULL-NEXT: mov.w r3, #-1
1310-
; FULL-NEXT: csel r0, r0, r3, ne
1308+
; FULL-NEXT: csinv r0, r0, zr, eq
13111309
; FULL-NEXT: csel r1, r1, r12, ne
1310+
; FULL-NEXT: csel r3, r3, lr, ne
13121311
; FULL-NEXT: csel r2, r2, lr, ne
13131312
; FULL-NEXT: rsbs r4, r0, #0
1314-
; FULL-NEXT: mov.w r12, #-2147483648
1315-
; FULL-NEXT: sbcs.w r4, r12, r1
1316-
; FULL-NEXT: sbcs.w r2, r3, r2
1317-
; FULL-NEXT: sbcs.w r2, r3, r5
1313+
; FULL-NEXT: mov.w lr, #-2147483648
1314+
; FULL-NEXT: sbcs.w r4, lr, r1
1315+
; FULL-NEXT: mov.w r12, #-1
1316+
; FULL-NEXT: sbcs.w r2, r12, r2
1317+
; FULL-NEXT: sbcs.w r2, r12, r3
13181318
; FULL-NEXT: it ge
13191319
; FULL-NEXT: movge r0, #0
1320-
; FULL-NEXT: csel r1, r1, r12, lt
1321-
; FULL-NEXT: pop {r4, r5, r7, pc}
1320+
; FULL-NEXT: csel r1, r1, lr, lt
1321+
; FULL-NEXT: pop {r4, pc}
13221322
entry:
13231323
%conv = fptosi float %x to i128
13241324
%0 = icmp slt i128 %conv, 9223372036854775807
@@ -1556,8 +1556,8 @@ define i64 @stest_f16i64(half %x) {
15561556
;
15571557
; FULL-LABEL: stest_f16i64:
15581558
; FULL: @ %bb.0: @ %entry
1559-
; FULL-NEXT: .save {r4, r5, r7, lr}
1560-
; FULL-NEXT: push {r4, r5, r7, lr}
1559+
; FULL-NEXT: .save {r4, lr}
1560+
; FULL-NEXT: push {r4, lr}
15611561
; FULL-NEXT: vmov.f16 r0, s0
15621562
; FULL-NEXT: vmov s0, r0
15631563
; FULL-NEXT: bl __fixhfti
@@ -1568,20 +1568,20 @@ define i64 @stest_f16i64(half %x) {
15681568
; FULL-NEXT: sbcs lr, r3, #0
15691569
; FULL-NEXT: cset lr, lt
15701570
; FULL-NEXT: cmp.w lr, #0
1571-
; FULL-NEXT: csel r5, r3, lr, ne
1572-
; FULL-NEXT: mov.w r3, #-1
1573-
; FULL-NEXT: csel r0, r0, r3, ne
1571+
; FULL-NEXT: csinv r0, r0, zr, eq
15741572
; FULL-NEXT: csel r1, r1, r12, ne
1573+
; FULL-NEXT: csel r3, r3, lr, ne
15751574
; FULL-NEXT: csel r2, r2, lr, ne
15761575
; FULL-NEXT: rsbs r4, r0, #0
1577-
; FULL-NEXT: mov.w r12, #-2147483648
1578-
; FULL-NEXT: sbcs.w r4, r12, r1
1579-
; FULL-NEXT: sbcs.w r2, r3, r2
1580-
; FULL-NEXT: sbcs.w r2, r3, r5
1576+
; FULL-NEXT: mov.w lr, #-2147483648
1577+
; FULL-NEXT: sbcs.w r4, lr, r1
1578+
; FULL-NEXT: mov.w r12, #-1
1579+
; FULL-NEXT: sbcs.w r2, r12, r2
1580+
; FULL-NEXT: sbcs.w r2, r12, r3
15811581
; FULL-NEXT: it ge
15821582
; FULL-NEXT: movge r0, #0
1583-
; FULL-NEXT: csel r1, r1, r12, lt
1584-
; FULL-NEXT: pop {r4, r5, r7, pc}
1583+
; FULL-NEXT: csel r1, r1, lr, lt
1584+
; FULL-NEXT: pop {r4, pc}
15851585
entry:
15861586
%conv = fptosi half %x to i128
15871587
%0 = icmp slt i128 %conv, 9223372036854775807
@@ -2708,8 +2708,8 @@ define i64 @stest_f64i64_mm(double %x) {
27082708
;
27092709
; FULL-LABEL: stest_f64i64_mm:
27102710
; FULL: @ %bb.0: @ %entry
2711-
; FULL-NEXT: .save {r4, r5, r7, lr}
2712-
; FULL-NEXT: push {r4, r5, r7, lr}
2711+
; FULL-NEXT: .save {r4, lr}
2712+
; FULL-NEXT: push {r4, lr}
27132713
; FULL-NEXT: bl __fixdfti
27142714
; FULL-NEXT: subs.w lr, r0, #-1
27152715
; FULL-NEXT: mvn r12, #-2147483648
@@ -2718,21 +2718,21 @@ define i64 @stest_f64i64_mm(double %x) {
27182718
; FULL-NEXT: sbcs lr, r3, #0
27192719
; FULL-NEXT: cset lr, lt
27202720
; FULL-NEXT: cmp.w lr, #0
2721-
; FULL-NEXT: csel r5, r3, lr, ne
2722-
; FULL-NEXT: mov.w r3, #-1
2723-
; FULL-NEXT: csel r0, r0, r3, ne
2721+
; FULL-NEXT: csinv r0, r0, zr, eq
27242722
; FULL-NEXT: csel r1, r1, r12, ne
2723+
; FULL-NEXT: csel r3, r3, lr, ne
27252724
; FULL-NEXT: csel r2, r2, lr, ne
27262725
; FULL-NEXT: rsbs r4, r0, #0
2727-
; FULL-NEXT: mov.w r12, #-2147483648
2728-
; FULL-NEXT: sbcs.w r4, r12, r1
2729-
; FULL-NEXT: sbcs.w r2, r3, r2
2730-
; FULL-NEXT: sbcs.w r2, r3, r5
2726+
; FULL-NEXT: mov.w lr, #-2147483648
2727+
; FULL-NEXT: sbcs.w r4, lr, r1
2728+
; FULL-NEXT: mov.w r12, #-1
2729+
; FULL-NEXT: sbcs.w r2, r12, r2
2730+
; FULL-NEXT: sbcs.w r2, r12, r3
27312731
; FULL-NEXT: cset r2, lt
27322732
; FULL-NEXT: cmp r2, #0
27332733
; FULL-NEXT: csel r0, r0, r2, ne
2734-
; FULL-NEXT: csel r1, r1, r12, ne
2735-
; FULL-NEXT: pop {r4, r5, r7, pc}
2734+
; FULL-NEXT: csel r1, r1, lr, ne
2735+
; FULL-NEXT: pop {r4, pc}
27362736
entry:
27372737
%conv = fptosi double %x to i128
27382738
%spec.store.select = call i128 @llvm.smin.i128(i128 %conv, i128 9223372036854775807)
@@ -3021,8 +3021,8 @@ define i64 @stest_f32i64_mm(float %x) {
30213021
;
30223022
; FULL-LABEL: stest_f32i64_mm:
30233023
; FULL: @ %bb.0: @ %entry
3024-
; FULL-NEXT: .save {r4, r5, r7, lr}
3025-
; FULL-NEXT: push {r4, r5, r7, lr}
3024+
; FULL-NEXT: .save {r4, lr}
3025+
; FULL-NEXT: push {r4, lr}
30263026
; FULL-NEXT: bl __fixsfti
30273027
; FULL-NEXT: subs.w lr, r0, #-1
30283028
; FULL-NEXT: mvn r12, #-2147483648
@@ -3031,21 +3031,21 @@ define i64 @stest_f32i64_mm(float %x) {
30313031
; FULL-NEXT: sbcs lr, r3, #0
30323032
; FULL-NEXT: cset lr, lt
30333033
; FULL-NEXT: cmp.w lr, #0
3034-
; FULL-NEXT: csel r5, r3, lr, ne
3035-
; FULL-NEXT: mov.w r3, #-1
3036-
; FULL-NEXT: csel r0, r0, r3, ne
3034+
; FULL-NEXT: csinv r0, r0, zr, eq
30373035
; FULL-NEXT: csel r1, r1, r12, ne
3036+
; FULL-NEXT: csel r3, r3, lr, ne
30383037
; FULL-NEXT: csel r2, r2, lr, ne
30393038
; FULL-NEXT: rsbs r4, r0, #0
3040-
; FULL-NEXT: mov.w r12, #-2147483648
3041-
; FULL-NEXT: sbcs.w r4, r12, r1
3042-
; FULL-NEXT: sbcs.w r2, r3, r2
3043-
; FULL-NEXT: sbcs.w r2, r3, r5
3039+
; FULL-NEXT: mov.w lr, #-2147483648
3040+
; FULL-NEXT: sbcs.w r4, lr, r1
3041+
; FULL-NEXT: mov.w r12, #-1
3042+
; FULL-NEXT: sbcs.w r2, r12, r2
3043+
; FULL-NEXT: sbcs.w r2, r12, r3
30443044
; FULL-NEXT: cset r2, lt
30453045
; FULL-NEXT: cmp r2, #0
30463046
; FULL-NEXT: csel r0, r0, r2, ne
3047-
; FULL-NEXT: csel r1, r1, r12, ne
3048-
; FULL-NEXT: pop {r4, r5, r7, pc}
3047+
; FULL-NEXT: csel r1, r1, lr, ne
3048+
; FULL-NEXT: pop {r4, pc}
30493049
entry:
30503050
%conv = fptosi float %x to i128
30513051
%spec.store.select = call i128 @llvm.smin.i128(i128 %conv, i128 9223372036854775807)
@@ -3339,8 +3339,8 @@ define i64 @stest_f16i64_mm(half %x) {
33393339
;
33403340
; FULL-LABEL: stest_f16i64_mm:
33413341
; FULL: @ %bb.0: @ %entry
3342-
; FULL-NEXT: .save {r4, r5, r7, lr}
3343-
; FULL-NEXT: push {r4, r5, r7, lr}
3342+
; FULL-NEXT: .save {r4, lr}
3343+
; FULL-NEXT: push {r4, lr}
33443344
; FULL-NEXT: vmov.f16 r0, s0
33453345
; FULL-NEXT: vmov s0, r0
33463346
; FULL-NEXT: bl __fixhfti
@@ -3351,21 +3351,21 @@ define i64 @stest_f16i64_mm(half %x) {
33513351
; FULL-NEXT: sbcs lr, r3, #0
33523352
; FULL-NEXT: cset lr, lt
33533353
; FULL-NEXT: cmp.w lr, #0
3354-
; FULL-NEXT: csel r5, r3, lr, ne
3355-
; FULL-NEXT: mov.w r3, #-1
3356-
; FULL-NEXT: csel r0, r0, r3, ne
3354+
; FULL-NEXT: csinv r0, r0, zr, eq
33573355
; FULL-NEXT: csel r1, r1, r12, ne
3356+
; FULL-NEXT: csel r3, r3, lr, ne
33583357
; FULL-NEXT: csel r2, r2, lr, ne
33593358
; FULL-NEXT: rsbs r4, r0, #0
3360-
; FULL-NEXT: mov.w r12, #-2147483648
3361-
; FULL-NEXT: sbcs.w r4, r12, r1
3362-
; FULL-NEXT: sbcs.w r2, r3, r2
3363-
; FULL-NEXT: sbcs.w r2, r3, r5
3359+
; FULL-NEXT: mov.w lr, #-2147483648
3360+
; FULL-NEXT: sbcs.w r4, lr, r1
3361+
; FULL-NEXT: mov.w r12, #-1
3362+
; FULL-NEXT: sbcs.w r2, r12, r2
3363+
; FULL-NEXT: sbcs.w r2, r12, r3
33643364
; FULL-NEXT: cset r2, lt
33653365
; FULL-NEXT: cmp r2, #0
33663366
; FULL-NEXT: csel r0, r0, r2, ne
3367-
; FULL-NEXT: csel r1, r1, r12, ne
3368-
; FULL-NEXT: pop {r4, r5, r7, pc}
3367+
; FULL-NEXT: csel r1, r1, lr, ne
3368+
; FULL-NEXT: pop {r4, pc}
33693369
entry:
33703370
%conv = fptosi half %x to i128
33713371
%spec.store.select = call i128 @llvm.smin.i128(i128 %conv, i128 9223372036854775807)

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