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[CodeGen] Use non-static Register::virtRegIndex() instead of static Register::virtReg2Index. NFC (#125031)
These are the the ones where we already had a Register object being used. Some places are still using unsigned which I did not convert.
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14 files changed

+36
-45
lines changed

14 files changed

+36
-45
lines changed

‎llvm/include/llvm/CodeGen/RegisterPressure.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -278,7 +278,7 @@ class LiveRegSet {
278278

279279
unsigned getSparseIndexFromReg(Register Reg) const {
280280
if (Reg.isVirtual())
281-
return Register::virtReg2Index(Reg) + NumRegUnits;
281+
return Reg.virtRegIndex() + NumRegUnits;
282282
assert(Reg < NumRegUnits);
283283
return Reg;
284284
}

‎llvm/include/llvm/CodeGen/TargetRegisterInfo.h‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1383,9 +1383,7 @@ class BitMaskClassIterator {
13831383
// This is useful when building IndexedMaps keyed on virtual registers
13841384
struct VirtReg2IndexFunctor {
13851385
using argument_type = Register;
1386-
unsigned operator()(Register Reg) const {
1387-
return Register::virtReg2Index(Reg);
1388-
}
1386+
unsigned operator()(Register Reg) const { return Reg.virtRegIndex(); }
13891387
};
13901388

13911389
/// Prints virtual and physical registers with or without a TRI instance.

‎llvm/lib/CodeGen/DetectDeadLanes.cpp‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -118,7 +118,7 @@ void DeadLaneDetector::addUsedLanesOnOperand(const MachineOperand &MO,
118118
UsedLanes = TRI->composeSubRegIndexLaneMask(MOSubReg, UsedLanes);
119119
UsedLanes &= MRI->getMaxLaneMaskForVReg(MOReg);
120120

121-
unsigned MORegIdx = Register::virtReg2Index(MOReg);
121+
unsigned MORegIdx = MOReg.virtRegIndex();
122122
DeadLaneDetector::VRegInfo &MORegInfo = VRegInfos[MORegIdx];
123123
LaneBitmask PrevUsedLanes = MORegInfo.UsedLanes;
124124
// Any change at all?
@@ -147,7 +147,7 @@ DeadLaneDetector::transferUsedLanes(const MachineInstr &MI,
147147
const MachineOperand &MO) const {
148148
unsigned OpNum = MO.getOperandNo();
149149
assert(lowersToCopies(MI) &&
150-
DefinedByCopy[Register::virtReg2Index(MI.getOperand(0).getReg())]);
150+
DefinedByCopy[MI.getOperand(0).getReg().virtRegIndex()]);
151151

152152
switch (MI.getOpcode()) {
153153
case TargetOpcode::COPY:
@@ -204,7 +204,7 @@ void DeadLaneDetector::transferDefinedLanesStep(const MachineOperand &Use,
204204
Register DefReg = Def.getReg();
205205
if (!DefReg.isVirtual())
206206
return;
207-
unsigned DefRegIdx = Register::virtReg2Index(DefReg);
207+
unsigned DefRegIdx = DefReg.virtRegIndex();
208208
if (!DefinedByCopy.test(DefRegIdx))
209209
return;
210210

@@ -433,7 +433,7 @@ bool DetectDeadLanes::isUndefInput(const DeadLaneDetector &DLD,
433433
Register DefReg = Def.getReg();
434434
if (!DefReg.isVirtual())
435435
return false;
436-
unsigned DefRegIdx = Register::virtReg2Index(DefReg);
436+
unsigned DefRegIdx = DefReg.virtRegIndex();
437437
if (!DLD.isDefinedByCopy(DefRegIdx))
438438
return false;
439439

@@ -506,7 +506,7 @@ DetectDeadLanes::modifySubRegisterOperandStatus(const DeadLaneDetector &DLD,
506506
Register Reg = MO.getReg();
507507
if (!Reg.isVirtual())
508508
continue;
509-
unsigned RegIdx = Register::virtReg2Index(Reg);
509+
unsigned RegIdx = Reg.virtRegIndex();
510510
const DeadLaneDetector::VRegInfo &RegInfo = DLD.getVRegInfo(RegIdx);
511511
if (MO.isDef() && !MO.isDead() && RegInfo.UsedLanes.none()) {
512512
LLVM_DEBUG(dbgs()

‎llvm/lib/CodeGen/InitUndef.cpp‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -142,8 +142,7 @@ bool InitUndef::handleSubReg(MachineFunction &MF, MachineInstr &MI,
142142
Register Reg = UseMO.getReg();
143143
if (NewRegs.count(Reg))
144144
continue;
145-
DeadLaneDetector::VRegInfo Info =
146-
DLD.getVRegInfo(Register::virtReg2Index(Reg));
145+
DeadLaneDetector::VRegInfo Info = DLD.getVRegInfo(Reg.virtRegIndex());
147146

148147
if (Info.UsedLanes == Info.DefinedLanes)
149148
continue;

‎llvm/lib/CodeGen/MachineVerifier.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3178,7 +3178,7 @@ struct VRegFilter {
31783178
for (Register Reg : FromRegSet) {
31793179
if (!Reg.isVirtual())
31803180
continue;
3181-
unsigned Index = Register::virtReg2Index(Reg);
3181+
unsigned Index = Reg.virtRegIndex();
31823182
if (Index < SparseUniverseMax) {
31833183
if (Index < SparseUniverse && Sparse.test(Index))
31843184
continue;
@@ -3201,7 +3201,7 @@ struct VRegFilter {
32013201
Dense.reserve(NewDenseSize);
32023202
for (unsigned I = Begin; I < End; ++I) {
32033203
Register Reg = ToVRegs[I];
3204-
unsigned Index = Register::virtReg2Index(Reg);
3204+
unsigned Index = Reg.virtRegIndex();
32053205
if (Index < SparseUniverseMax)
32063206
Sparse.set(Index);
32073207
else

‎llvm/lib/CodeGen/RegAllocFast.cpp‎

Lines changed: 10 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -207,9 +207,7 @@ class RegAllocFastImpl {
207207

208208
explicit LiveReg(Register VirtReg) : VirtReg(VirtReg) {}
209209

210-
unsigned getSparseSetIndex() const {
211-
return Register::virtReg2Index(VirtReg);
212-
}
210+
unsigned getSparseSetIndex() const { return VirtReg.virtRegIndex(); }
213211
};
214212

215213
using LiveRegMap = SparseSet<LiveReg, identity<unsigned>, uint16_t>;
@@ -349,11 +347,11 @@ class RegAllocFastImpl {
349347
unsigned calcSpillCost(MCPhysReg PhysReg) const;
350348

351349
LiveRegMap::iterator findLiveVirtReg(Register VirtReg) {
352-
return LiveVirtRegs.find(Register::virtReg2Index(VirtReg));
350+
return LiveVirtRegs.find(VirtReg.virtRegIndex());
353351
}
354352

355353
LiveRegMap::const_iterator findLiveVirtReg(Register VirtReg) const {
356-
return LiveVirtRegs.find(Register::virtReg2Index(VirtReg));
354+
return LiveVirtRegs.find(VirtReg.virtRegIndex());
357355
}
358356

359357
void assignVirtToPhysReg(MachineInstr &MI, LiveReg &, MCPhysReg PhysReg);
@@ -493,7 +491,7 @@ static bool dominates(InstrPosIndexes &PosIndexes, const MachineInstr &A,
493491

494492
/// Returns false if \p VirtReg is known to not live out of the current block.
495493
bool RegAllocFastImpl::mayLiveOut(Register VirtReg) {
496-
if (MayLiveAcrossBlocks.test(Register::virtReg2Index(VirtReg))) {
494+
if (MayLiveAcrossBlocks.test(VirtReg.virtRegIndex())) {
497495
// Cannot be live-out if there are no successors.
498496
return !MBB->succ_empty();
499497
}
@@ -506,15 +504,15 @@ bool RegAllocFastImpl::mayLiveOut(Register VirtReg) {
506504
// Find the first def in the self loop MBB.
507505
for (const MachineInstr &DefInst : MRI->def_instructions(VirtReg)) {
508506
if (DefInst.getParent() != MBB) {
509-
MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg));
507+
MayLiveAcrossBlocks.set(VirtReg.virtRegIndex());
510508
return true;
511509
} else {
512510
if (!SelfLoopDef || dominates(PosIndexes, DefInst, *SelfLoopDef))
513511
SelfLoopDef = &DefInst;
514512
}
515513
}
516514
if (!SelfLoopDef) {
517-
MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg));
515+
MayLiveAcrossBlocks.set(VirtReg.virtRegIndex());
518516
return true;
519517
}
520518
}
@@ -525,7 +523,7 @@ bool RegAllocFastImpl::mayLiveOut(Register VirtReg) {
525523
unsigned C = 0;
526524
for (const MachineInstr &UseInst : MRI->use_nodbg_instructions(VirtReg)) {
527525
if (UseInst.getParent() != MBB || ++C >= Limit) {
528-
MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg));
526+
MayLiveAcrossBlocks.set(VirtReg.virtRegIndex());
529527
// Cannot be live-out if there are no successors.
530528
return !MBB->succ_empty();
531529
}
@@ -535,7 +533,7 @@ bool RegAllocFastImpl::mayLiveOut(Register VirtReg) {
535533
// value inside a self looping block.
536534
if (SelfLoopDef == &UseInst ||
537535
!dominates(PosIndexes, *SelfLoopDef, UseInst)) {
538-
MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg));
536+
MayLiveAcrossBlocks.set(VirtReg.virtRegIndex());
539537
return true;
540538
}
541539
}
@@ -546,15 +544,15 @@ bool RegAllocFastImpl::mayLiveOut(Register VirtReg) {
546544

547545
/// Returns false if \p VirtReg is known to not be live into the current block.
548546
bool RegAllocFastImpl::mayLiveIn(Register VirtReg) {
549-
if (MayLiveAcrossBlocks.test(Register::virtReg2Index(VirtReg)))
547+
if (MayLiveAcrossBlocks.test(VirtReg.virtRegIndex()))
550548
return !MBB->pred_empty();
551549

552550
// See if the first \p Limit def of the register are all in the current block.
553551
static const unsigned Limit = 8;
554552
unsigned C = 0;
555553
for (const MachineInstr &DefInst : MRI->def_instructions(VirtReg)) {
556554
if (DefInst.getParent() != MBB || ++C >= Limit) {
557-
MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg));
555+
MayLiveAcrossBlocks.set(VirtReg.virtRegIndex());
558556
return !MBB->pred_empty();
559557
}
560558
}

‎llvm/lib/CodeGen/RegisterScavenging.cpp‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -412,8 +412,7 @@ static bool scavengeFrameVirtualRegsInBlock(MachineRegisterInfo &MRI,
412412
// We only care about virtual registers and ignore virtual registers
413413
// created by the target callbacks in the process (those will be handled
414414
// in a scavenging round).
415-
if (!Reg.isVirtual() ||
416-
Register::virtReg2Index(Reg) >= InitialNumVirtRegs)
415+
if (!Reg.isVirtual() || Reg.virtRegIndex() >= InitialNumVirtRegs)
417416
continue;
418417
if (!MO.readsReg())
419418
continue;
@@ -432,8 +431,7 @@ static bool scavengeFrameVirtualRegsInBlock(MachineRegisterInfo &MRI,
432431
continue;
433432
Register Reg = MO.getReg();
434433
// Only vregs, no newly created vregs (see above).
435-
if (!Reg.isVirtual() ||
436-
Register::virtReg2Index(Reg) >= InitialNumVirtRegs)
434+
if (!Reg.isVirtual() || Reg.virtRegIndex() >= InitialNumVirtRegs)
437435
continue;
438436
// We have to look at all operands anyway so we can precalculate here
439437
// whether there is a reading operand. This allows use to skip the use

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -698,7 +698,7 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
698698
Def->getParent()->insert(std::next(InsertPos), MI);
699699
} else
700700
LLVM_DEBUG(dbgs() << "Dropping debug info for dead vreg"
701-
<< Register::virtReg2Index(Reg) << "\n");
701+
<< printReg(Reg) << '\n');
702702
}
703703

704704
// Don't try and extend through copies in instruction referencing mode.

‎llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -284,9 +284,8 @@ std::optional<int> AArch64StackTaggingPreRA::findFirstSlotCandidate() {
284284
WorkList.push_back(DstReg);
285285
continue;
286286
}
287-
LLVM_DEBUG(dbgs() << "[" << ST.FI << ":" << ST.Tag << "] use of %"
288-
<< Register::virtReg2Index(UseReg) << " in " << UseI
289-
<< "\n");
287+
LLVM_DEBUG(dbgs() << "[" << ST.FI << ":" << ST.Tag << "] use of "
288+
<< printReg(UseReg) << " in " << UseI << "\n");
290289
Score++;
291290
}
292291
}

‎llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -264,7 +264,7 @@ void HexagonSplitDoubleRegs::partitionRegisters(UUSetMap &P2Rs) {
264264
}
265265
if (MRI->getRegClass(T) != DoubleRC)
266266
continue;
267-
unsigned u = Register::virtReg2Index(T);
267+
unsigned u = T.virtRegIndex();
268268
if (FixedRegs[u])
269269
continue;
270270
LLVM_DEBUG(dbgs() << ' ' << printReg(T, TRI));

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