[GlobalISel][AMDGPU] Update tests

Change-Id: I28f0273da90b5caa9133762ab272ede95a7dd82e

Author: chinmaydd

llvm/test/CodeGen/AMDGPU/GlobalISel/and.ll

@@ -834,6 +834,140 @@ define amdgpu_kernel void @s_and_u64_sext_with_sregs(ptr addrspace(1) %out, ptr
   store i64 %and, ptr addrspace(1) %out, align 8
   ret void
 }
+
+define <2 x i128> @v_and_v2i128(<2 x i128> %a, <2 x i128> %b) {
+; GFX7-LABEL: v_and_v2i128:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_and_b32_e32 v0, v0, v8
+; GFX7-NEXT:    v_and_b32_e32 v1, v1, v9
+; GFX7-NEXT:    v_and_b32_e32 v2, v2, v10
+; GFX7-NEXT:    v_and_b32_e32 v3, v3, v11
+; GFX7-NEXT:    v_and_b32_e32 v4, v4, v12
+; GFX7-NEXT:    v_and_b32_e32 v5, v5, v13
+; GFX7-NEXT:    v_and_b32_e32 v6, v6, v14
+; GFX7-NEXT:    v_and_b32_e32 v7, v7, v15
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_and_v2i128:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_and_b32_e32 v0, v0, v8
+; GFX9-NEXT:    v_and_b32_e32 v1, v1, v9
+; GFX9-NEXT:    v_and_b32_e32 v2, v2, v10
+; GFX9-NEXT:    v_and_b32_e32 v3, v3, v11
+; GFX9-NEXT:    v_and_b32_e32 v4, v4, v12
+; GFX9-NEXT:    v_and_b32_e32 v5, v5, v13
+; GFX9-NEXT:    v_and_b32_e32 v6, v6, v14
+; GFX9-NEXT:    v_and_b32_e32 v7, v7, v15
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_and_v2i128:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_and_b32_e32 v0, v0, v8
+; GFX8-NEXT:    v_and_b32_e32 v1, v1, v9
+; GFX8-NEXT:    v_and_b32_e32 v2, v2, v10
+; GFX8-NEXT:    v_and_b32_e32 v3, v3, v11
+; GFX8-NEXT:    v_and_b32_e32 v4, v4, v12
+; GFX8-NEXT:    v_and_b32_e32 v5, v5, v13
+; GFX8-NEXT:    v_and_b32_e32 v6, v6, v14
+; GFX8-NEXT:    v_and_b32_e32 v7, v7, v15
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_and_v2i128:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_and_b32_e32 v0, v0, v8
+; GFX10-NEXT:    v_and_b32_e32 v1, v1, v9
+; GFX10-NEXT:    v_and_b32_e32 v2, v2, v10
+; GFX10-NEXT:    v_and_b32_e32 v3, v3, v11
+; GFX10-NEXT:    v_and_b32_e32 v4, v4, v12
+; GFX10-NEXT:    v_and_b32_e32 v5, v5, v13
+; GFX10-NEXT:    v_and_b32_e32 v6, v6, v14
+; GFX10-NEXT:    v_and_b32_e32 v7, v7, v15
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_and_v2i128:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_and_b32_e32 v0, v0, v8
+; GFX11-NEXT:    v_and_b32_e32 v1, v1, v9
+; GFX11-NEXT:    v_and_b32_e32 v2, v2, v10
+; GFX11-NEXT:    v_and_b32_e32 v3, v3, v11
+; GFX11-NEXT:    v_and_b32_e32 v4, v4, v12
+; GFX11-NEXT:    v_and_b32_e32 v5, v5, v13
+; GFX11-NEXT:    v_and_b32_e32 v6, v6, v14
+; GFX11-NEXT:    v_and_b32_e32 v7, v7, v15
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+  %and = and <2 x i128> %a, %b
+  ret <2 x i128> %and
+}
+
+define <2 x i128> @v_and_v2i128_inline_imm(<2 x i128> %a) {
+; GFX7-LABEL: v_and_v2i128_inline_imm:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_and_b32_e32 v0, 64, v0
+; GFX7-NEXT:    v_and_b32_e32 v4, 64, v4
+; GFX7-NEXT:    v_mov_b32_e32 v1, 0
+; GFX7-NEXT:    v_mov_b32_e32 v2, 0
+; GFX7-NEXT:    v_mov_b32_e32 v3, 0
+; GFX7-NEXT:    v_mov_b32_e32 v5, 0
+; GFX7-NEXT:    v_mov_b32_e32 v6, 0
+; GFX7-NEXT:    v_mov_b32_e32 v7, 0
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_and_v2i128_inline_imm:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_and_b32_e32 v0, 64, v0
+; GFX9-NEXT:    v_and_b32_e32 v4, 64, v4
+; GFX9-NEXT:    v_mov_b32_e32 v1, 0
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0
+; GFX9-NEXT:    v_mov_b32_e32 v3, 0
+; GFX9-NEXT:    v_mov_b32_e32 v5, 0
+; GFX9-NEXT:    v_mov_b32_e32 v6, 0
+; GFX9-NEXT:    v_mov_b32_e32 v7, 0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_and_v2i128_inline_imm:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_and_b32_e32 v0, 64, v0
+; GFX8-NEXT:    v_and_b32_e32 v4, 64, v4
+; GFX8-NEXT:    v_mov_b32_e32 v1, 0
+; GFX8-NEXT:    v_mov_b32_e32 v2, 0
+; GFX8-NEXT:    v_mov_b32_e32 v3, 0
+; GFX8-NEXT:    v_mov_b32_e32 v5, 0
+; GFX8-NEXT:    v_mov_b32_e32 v6, 0
+; GFX8-NEXT:    v_mov_b32_e32 v7, 0
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_and_v2i128_inline_imm:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_and_b32_e32 v0, 64, v0
+; GFX10-NEXT:    v_and_b32_e32 v4, 64, v4
+; GFX10-NEXT:    v_mov_b32_e32 v1, 0
+; GFX10-NEXT:    v_mov_b32_e32 v2, 0
+; GFX10-NEXT:    v_mov_b32_e32 v3, 0
+; GFX10-NEXT:    v_mov_b32_e32 v5, 0
+; GFX10-NEXT:    v_mov_b32_e32 v6, 0
+; GFX10-NEXT:    v_mov_b32_e32 v7, 0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_and_v2i128_inline_imm:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 64, v0
+; GFX11-NEXT:    v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v4, 64, v4
+; GFX11-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
+; GFX11-NEXT:    v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v7, 0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+  %and = and <2 x i128> %a, <i128 64, i128 64>
+  ret <2 x i128> %and
+}
 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
 ; GFX11-FAKE16: {{.*}}
 ; GFX11-TRUE16: {{.*}}

llvm/test/CodeGen/AMDGPU/GlobalISel/and.v2i128.ll

@@ -838,6 +838,114 @@ define amdgpu_kernel void @s_or_u64_sext_with_sregs(ptr addrspace(1) %out, ptr a
   store i64 %or, ptr addrspace(1) %out, align 8
   ret void
 }
+
+define <2 x i128> @v_or_v2i128(<2 x i128> %a, <2 x i128> %b) {
+; GFX7-LABEL: v_or_v2i128:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_or_b32_e32 v0, v0, v8
+; GFX7-NEXT:    v_or_b32_e32 v1, v1, v9
+; GFX7-NEXT:    v_or_b32_e32 v2, v2, v10
+; GFX7-NEXT:    v_or_b32_e32 v3, v3, v11
+; GFX7-NEXT:    v_or_b32_e32 v4, v4, v12
+; GFX7-NEXT:    v_or_b32_e32 v5, v5, v13
+; GFX7-NEXT:    v_or_b32_e32 v6, v6, v14
+; GFX7-NEXT:    v_or_b32_e32 v7, v7, v15
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_or_v2i128:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_or_b32_e32 v0, v0, v8
+; GFX9-NEXT:    v_or_b32_e32 v1, v1, v9
+; GFX9-NEXT:    v_or_b32_e32 v2, v2, v10
+; GFX9-NEXT:    v_or_b32_e32 v3, v3, v11
+; GFX9-NEXT:    v_or_b32_e32 v4, v4, v12
+; GFX9-NEXT:    v_or_b32_e32 v5, v5, v13
+; GFX9-NEXT:    v_or_b32_e32 v6, v6, v14
+; GFX9-NEXT:    v_or_b32_e32 v7, v7, v15
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_or_v2i128:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_or_b32_e32 v0, v0, v8
+; GFX8-NEXT:    v_or_b32_e32 v1, v1, v9
+; GFX8-NEXT:    v_or_b32_e32 v2, v2, v10
+; GFX8-NEXT:    v_or_b32_e32 v3, v3, v11
+; GFX8-NEXT:    v_or_b32_e32 v4, v4, v12
+; GFX8-NEXT:    v_or_b32_e32 v5, v5, v13
+; GFX8-NEXT:    v_or_b32_e32 v6, v6, v14
+; GFX8-NEXT:    v_or_b32_e32 v7, v7, v15
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_or_v2i128:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_or_b32_e32 v0, v0, v8
+; GFX10-NEXT:    v_or_b32_e32 v1, v1, v9
+; GFX10-NEXT:    v_or_b32_e32 v2, v2, v10
+; GFX10-NEXT:    v_or_b32_e32 v3, v3, v11
+; GFX10-NEXT:    v_or_b32_e32 v4, v4, v12
+; GFX10-NEXT:    v_or_b32_e32 v5, v5, v13
+; GFX10-NEXT:    v_or_b32_e32 v6, v6, v14
+; GFX10-NEXT:    v_or_b32_e32 v7, v7, v15
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_or_v2i128:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_or_b32_e32 v0, v0, v8
+; GFX11-NEXT:    v_or_b32_e32 v1, v1, v9
+; GFX11-NEXT:    v_or_b32_e32 v2, v2, v10
+; GFX11-NEXT:    v_or_b32_e32 v3, v3, v11
+; GFX11-NEXT:    v_or_b32_e32 v4, v4, v12
+; GFX11-NEXT:    v_or_b32_e32 v5, v5, v13
+; GFX11-NEXT:    v_or_b32_e32 v6, v6, v14
+; GFX11-NEXT:    v_or_b32_e32 v7, v7, v15
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+  %or = or <2 x i128> %a, %b
+  ret <2 x i128> %or
+}
+
+define <2 x i128> @v_or_v2i128_inline_imm(<2 x i128> %a) {
+; GFX7-LABEL: v_or_v2i128_inline_imm:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_or_b32_e32 v0, 64, v0
+; GFX7-NEXT:    v_or_b32_e32 v4, 64, v4
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_or_v2i128_inline_imm:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_or_b32_e32 v0, 64, v0
+; GFX9-NEXT:    v_or_b32_e32 v4, 64, v4
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_or_v2i128_inline_imm:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_or_b32_e32 v0, 64, v0
+; GFX8-NEXT:    v_or_b32_e32 v4, 64, v4
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_or_v2i128_inline_imm:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_or_b32_e32 v0, 64, v0
+; GFX10-NEXT:    v_or_b32_e32 v4, 64, v4
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_or_v2i128_inline_imm:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_or_b32_e32 v0, 64, v0
+; GFX11-NEXT:    v_or_b32_e32 v4, 64, v4
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+  %or = or <2 x i128> %a, <i128 64, i128 64>
+  ret <2 x i128> %or
+}
 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
 ; GFX11-FAKE16: {{.*}}
 ; GFX11-TRUE16: {{.*}}