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[GISel][RISCV] Add G_SMIN/SMAX/UMIN/UMAX to GISelKnownBits::computeNumSignBits. (#116321)
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6 files changed

+18
-22
lines changed

6 files changed

+18
-22
lines changed

‎llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -789,6 +789,14 @@ unsigned GISelKnownBits::computeNumSignBits(Register R,
789789
MI.getOperand(3).getReg(), DemandedElts,
790790
Depth + 1);
791791
}
792+
case TargetOpcode::G_SMIN:
793+
case TargetOpcode::G_SMAX:
794+
case TargetOpcode::G_UMIN:
795+
case TargetOpcode::G_UMAX:
796+
// TODO: Handle clamp pattern with number of sign bits for SMIN/SMAX.
797+
return computeNumSignBitsMin(MI.getOperand(1).getReg(),
798+
MI.getOperand(2).getReg(), DemandedElts,
799+
Depth + 1);
792800
case TargetOpcode::G_SADDO:
793801
case TargetOpcode::G_SADDE:
794802
case TargetOpcode::G_UADDO:

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smax-rv32.mir‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -28,8 +28,7 @@ body: |
2828
; RV32ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
2929
; RV32ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
3030
; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
31-
; RV32ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SMAX]], 8
32-
; RV32ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s32)
31+
; RV32ZBB-NEXT: $x10 = COPY [[SMAX]](s32)
3332
; RV32ZBB-NEXT: PseudoRET implicit $x10
3433
%0:_(s32) = COPY $x10
3534
%1:_(s32) = COPY $x11
@@ -66,8 +65,7 @@ body: |
6665
; RV32ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
6766
; RV32ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
6867
; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
69-
; RV32ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SMAX]], 16
70-
; RV32ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s32)
68+
; RV32ZBB-NEXT: $x10 = COPY [[SMAX]](s32)
7169
; RV32ZBB-NEXT: PseudoRET implicit $x10
7270
%0:_(s32) = COPY $x10
7371
%1:_(s32) = COPY $x11

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smax-rv64.mir‎

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -31,8 +31,7 @@ body: |
3131
; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 8
3232
; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 8
3333
; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
34-
; RV64ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SMAX]], 8
35-
; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s64)
34+
; RV64ZBB-NEXT: $x10 = COPY [[SMAX]](s64)
3635
; RV64ZBB-NEXT: PseudoRET implicit $x10
3736
%0:_(s64) = COPY $x10
3837
%1:_(s64) = COPY $x11
@@ -72,8 +71,7 @@ body: |
7271
; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 16
7372
; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 16
7473
; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
75-
; RV64ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SMAX]], 16
76-
; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s64)
74+
; RV64ZBB-NEXT: $x10 = COPY [[SMAX]](s64)
7775
; RV64ZBB-NEXT: PseudoRET implicit $x10
7876
%0:_(s64) = COPY $x10
7977
%1:_(s64) = COPY $x11
@@ -108,8 +106,7 @@ body: |
108106
; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
109107
; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
110108
; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
111-
; RV64ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SMAX]], 32
112-
; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s64)
109+
; RV64ZBB-NEXT: $x10 = COPY [[SMAX]](s64)
113110
; RV64ZBB-NEXT: PseudoRET implicit $x10
114111
%0:_(s64) = COPY $x10
115112
%1:_(s64) = COPY $x11

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smin-rv32.mir‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -28,8 +28,7 @@ body: |
2828
; RV32ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
2929
; RV32ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
3030
; RV32ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
31-
; RV32ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SMIN]], 8
32-
; RV32ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s32)
31+
; RV32ZBB-NEXT: $x10 = COPY [[SMIN]](s32)
3332
; RV32ZBB-NEXT: PseudoRET implicit $x10
3433
%0:_(s32) = COPY $x10
3534
%1:_(s32) = COPY $x11
@@ -66,8 +65,7 @@ body: |
6665
; RV32ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
6766
; RV32ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
6867
; RV32ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
69-
; RV32ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SMIN]], 16
70-
; RV32ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s32)
68+
; RV32ZBB-NEXT: $x10 = COPY [[SMIN]](s32)
7169
; RV32ZBB-NEXT: PseudoRET implicit $x10
7270
%0:_(s32) = COPY $x10
7371
%1:_(s32) = COPY $x11

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smin-rv64.mir‎

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -31,8 +31,7 @@ body: |
3131
; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 8
3232
; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 8
3333
; RV64ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
34-
; RV64ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SMIN]], 8
35-
; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s64)
34+
; RV64ZBB-NEXT: $x10 = COPY [[SMIN]](s64)
3635
; RV64ZBB-NEXT: PseudoRET implicit $x10
3736
%0:_(s64) = COPY $x10
3837
%1:_(s64) = COPY $x11
@@ -72,8 +71,7 @@ body: |
7271
; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 16
7372
; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 16
7473
; RV64ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
75-
; RV64ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SMIN]], 16
76-
; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s64)
74+
; RV64ZBB-NEXT: $x10 = COPY [[SMIN]](s64)
7775
; RV64ZBB-NEXT: PseudoRET implicit $x10
7876
%0:_(s64) = COPY $x10
7977
%1:_(s64) = COPY $x11
@@ -108,8 +106,7 @@ body: |
108106
; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
109107
; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
110108
; RV64ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
111-
; RV64ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SMIN]], 32
112-
; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s64)
109+
; RV64ZBB-NEXT: $x10 = COPY [[SMIN]](s64)
113110
; RV64ZBB-NEXT: PseudoRET implicit $x10
114111
%0:_(s64) = COPY $x10
115112
%1:_(s64) = COPY $x11

‎llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -929,7 +929,6 @@ define signext i32 @min_i32(i32 signext %a, i32 signext %b) nounwind {
929929
; RV64ZBB-LABEL: min_i32:
930930
; RV64ZBB: # %bb.0:
931931
; RV64ZBB-NEXT: min a0, a0, a1
932-
; RV64ZBB-NEXT: sext.w a0, a0
933932
; RV64ZBB-NEXT: ret
934933
%cmp = icmp slt i32 %a, %b
935934
%cond = select i1 %cmp, i32 %a, i32 %b
@@ -967,7 +966,6 @@ define signext i32 @max_i32(i32 signext %a, i32 signext %b) nounwind {
967966
; RV64ZBB-LABEL: max_i32:
968967
; RV64ZBB: # %bb.0:
969968
; RV64ZBB-NEXT: max a0, a0, a1
970-
; RV64ZBB-NEXT: sext.w a0, a0
971969
; RV64ZBB-NEXT: ret
972970
%cmp = icmp sgt i32 %a, %b
973971
%cond = select i1 %cmp, i32 %a, i32 %b

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