On newer targets, revert back to using s_cmp

Author: vangthao95

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

@@ -222,12 +222,20 @@ bool AMDGPUInstructionSelector::selectCOPY_SCC_VCC(MachineInstr &I) const {
   const DebugLoc &DL = I.getDebugLoc();
   MachineBasicBlock *BB = I.getParent();
   Register VCCReg = I.getOperand(1).getReg();
+  MachineInstr *Cmp;
 
-  unsigned Opc = STI.isWave64() ? AMDGPU::S_OR_B64 : AMDGPU::S_OR_B32;
-  Register DeadDst = MRI->createVirtualRegister(
-      STI.isWave64() ? &AMDGPU::SReg_64RegClass : &AMDGPU::SReg_32RegClass);
-  MachineInstr *Cmp =
-      BuildMI(*BB, &I, DL, TII.get(Opc), DeadDst).addReg(VCCReg).addReg(VCCReg);
+  if (STI.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
+    unsigned CmpOpc =
+        STI.isWave64() ? AMDGPU::S_CMP_LG_U64 : AMDGPU::S_CMP_LG_U32;
+    Cmp = BuildMI(*BB, &I, DL, TII.get(CmpOpc)).addReg(VCCReg).addImm(0);
+  } else {
+    // For gfx7 and earlier, S_CMP_LG_U64 doesn't exist, so we use S_OR_B64
+    // which sets SCC as a side effect.
+    Register DeadDst = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass);
+    Cmp = BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_OR_B64), DeadDst)
+              .addReg(VCCReg)
+              .addReg(VCCReg);
+  }
 
   if (!constrainSelectedInstRegOperands(*Cmp, TII, TRI, RBI))
     return false;

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy-scc-vcc.ll

@@ -29,7 +29,7 @@ define amdgpu_kernel void @fcmp_uniform_select(float %a, i32 %b, i32 %c, ptr add
 ; GFX8-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0x34
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    v_cmp_eq_f32_e64 s[4:5], s0, 0
-; GFX8-NEXT:    s_or_b64 s[4:5], s[4:5], s[4:5]
+; GFX8-NEXT:    s_cmp_lg_u64 s[4:5], 0
 ; GFX8-NEXT:    s_cselect_b32 s0, 1, 0
 ; GFX8-NEXT:    s_and_b32 s0, s0, 1
 ; GFX8-NEXT:    s_cmp_lg_u32 s0, 0
@@ -49,7 +49,7 @@ define amdgpu_kernel void @fcmp_uniform_select(float %a, i32 %b, i32 %c, ptr add
 ; GFX11-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11-NEXT:    v_cmp_eq_f32_e64 s0, s0, 0
-; GFX11-NEXT:    s_or_b32 s0, s0, s0
+; GFX11-NEXT:    s_cmp_lg_u32 s0, 0
 ; GFX11-NEXT:    s_cselect_b32 s0, 1, 0
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
 ; GFX11-NEXT:    s_and_b32 s0, s0, 1

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy-scc-vcc.mir

@@ -1,6 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx700 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GFX %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx803 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GFX %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx700 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GFX7 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx803 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GF8 %s
 # RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GFX11 %s
 
 ---
@@ -10,16 +10,23 @@ regBankSelected: true
 tracksRegLiveness: true
 body: |
   bb.0:
-    ; GFX-LABEL: name: test_copy_scc_vcc
-    ; GFX: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
-    ; GFX-NEXT: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[DEF]], [[DEF]], implicit-def $scc
-    ; GFX-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $scc
-    ; GFX-NEXT: $sgpr0 = COPY [[COPY]]
-    ; GFX-NEXT: S_ENDPGM 0, implicit $sgpr0
+    ; GFX7-LABEL: name: test_copy_scc_vcc
+    ; GFX7: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
+    ; GFX7-NEXT: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[DEF]], [[DEF]], implicit-def $scc
+    ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $scc
+    ; GFX7-NEXT: $sgpr0 = COPY [[COPY]]
+    ; GFX7-NEXT: S_ENDPGM 0, implicit $sgpr0
+    ;
+    ; GF8-LABEL: name: test_copy_scc_vcc
+    ; GF8: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
+    ; GF8-NEXT: S_CMP_LG_U64 [[DEF]], 0, implicit-def $scc
+    ; GF8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $scc
+    ; GF8-NEXT: $sgpr0 = COPY [[COPY]]
+    ; GF8-NEXT: S_ENDPGM 0, implicit $sgpr0
     ;
     ; GFX11-LABEL: name: test_copy_scc_vcc
     ; GFX11: [[DEF:%[0-9]+]]:sreg_32_xm0_xexec = IMPLICIT_DEF
-    ; GFX11-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[DEF]], [[DEF]], implicit-def $scc
+    ; GFX11-NEXT: S_CMP_LG_U32 [[DEF]], 0, implicit-def $scc
     ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $scc
     ; GFX11-NEXT: $sgpr0 = COPY [[COPY]]
     ; GFX11-NEXT: S_ENDPGM 0, implicit $sgpr0

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll

@@ -210,7 +210,7 @@ define amdgpu_ps void @vcc_to_scc(float inreg %a, i32 inreg %b, i32 inreg %c, pt
 ; NEW_RBS-LABEL: vcc_to_scc:
 ; NEW_RBS:       ; %bb.0:
 ; NEW_RBS-NEXT:    v_cmp_eq_f32_e64 s0, s0, 0
-; NEW_RBS-NEXT:    s_or_b32 s0, s0, s0
+; NEW_RBS-NEXT:    s_cmp_lg_u32 s0, 0
 ; NEW_RBS-NEXT:    s_cselect_b32 s0, 1, 0
 ; NEW_RBS-NEXT:    s_and_b32 s0, s0, 1
 ; NEW_RBS-NEXT:    s_cmp_lg_u32 s0, 0