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Ana MihajlovicAna Mihajlovic
Ana Mihajlovic
authored and
Ana Mihajlovic
committed
add i32 and i64
1 parent ee340d6 commit 47b2325

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5 files changed

+228
-55
lines changed

5 files changed

+228
-55
lines changed

‎llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp‎

Lines changed: 39 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -838,6 +838,32 @@ bool SIShrinkInstructions::tryReplaceDeadSDST(MachineInstr &MI) const {
838838

839839
unsigned SIShrinkInstructions::getInverseCompareOpcode(MachineInstr &MI) const {
840840
switch (MI.getOpcode()) {
841+
// int 32
842+
case AMDGPU::V_CMP_EQ_I32_e64:
843+
return AMDGPU::V_CMP_NE_I32_e64;
844+
case AMDGPU::V_CMP_NE_I32_e64:
845+
return AMDGPU::V_CMP_EQ_I32_e64;
846+
case AMDGPU::V_CMP_GE_I32_e64:
847+
return AMDGPU::V_CMP_LT_I32_e64;
848+
case AMDGPU::V_CMP_LE_I32_e64:
849+
return AMDGPU::V_CMP_GT_I32_e64;
850+
case AMDGPU::V_CMP_GT_I32_e64:
851+
return AMDGPU::V_CMP_LE_I32_e64;
852+
case AMDGPU::V_CMP_LT_I32_e64:
853+
return AMDGPU::V_CMP_GE_I32_e64;
854+
// int 64
855+
case AMDGPU::V_CMP_EQ_I64_e64:
856+
return AMDGPU::V_CMP_NE_I64_e64;
857+
case AMDGPU::V_CMP_NE_I64_e64:
858+
return AMDGPU::V_CMP_EQ_I64_e64;
859+
case AMDGPU::V_CMP_GE_I64_e64:
860+
return AMDGPU::V_CMP_LT_I64_e64;
861+
case AMDGPU::V_CMP_LE_I64_e64:
862+
return AMDGPU::V_CMP_GT_I64_e64;
863+
case AMDGPU::V_CMP_GT_I64_e64:
864+
return AMDGPU::V_CMP_LE_I64_e64;
865+
case AMDGPU::V_CMP_LT_I64_e64:
866+
return AMDGPU::V_CMP_GE_I64_e64;
841867
// unsigned 32
842868
case AMDGPU::V_CMP_EQ_U32_e64:
843869
return AMDGPU::V_CMP_NE_U32_e64;
@@ -875,8 +901,8 @@ unsigned SIShrinkInstructions::getInverseCompareOpcode(MachineInstr &MI) const {
875901
return AMDGPU::V_CMP_GE_F32_e64;
876902
case AMDGPU::V_CMP_LE_F32_e64:
877903
return AMDGPU::V_CMP_NLE_F32_e64;
878-
case AMDGPU::V_CMP_NLE_F32_e32:
879-
return AMDGPU::V_CMP_LE_F32_e32;
904+
case AMDGPU::V_CMP_NLE_F32_e64:
905+
return AMDGPU::V_CMP_LE_F32_e64;
880906
case AMDGPU::V_CMP_GT_F32_e64:
881907
return AMDGPU::V_CMP_NGT_F32_e64;
882908
case AMDGPU::V_CMP_NGT_F32_e64:
@@ -904,8 +930,8 @@ unsigned SIShrinkInstructions::getInverseCompareOpcode(MachineInstr &MI) const {
904930
return AMDGPU::V_CMP_GE_F64_e64;
905931
case AMDGPU::V_CMP_LE_F64_e64:
906932
return AMDGPU::V_CMP_NLE_F64_e64;
907-
case AMDGPU::V_CMP_NLE_F64_e32:
908-
return AMDGPU::V_CMP_LE_F64_e32;
933+
case AMDGPU::V_CMP_NLE_F64_e64:
934+
return AMDGPU::V_CMP_LE_F64_e64;
909935
case AMDGPU::V_CMP_GT_F64_e64:
910936
return AMDGPU::V_CMP_NGT_F64_e64;
911937
case AMDGPU::V_CMP_NGT_F64_e64:
@@ -930,27 +956,28 @@ unsigned SIShrinkInstructions::getInverseCompareOpcode(MachineInstr &MI) const {
930956
bool SIShrinkInstructions::shouldSwapCndOperands(
931957
MachineInstr &MI, SmallVector<MachineOperand *, 4> &UsesToProcess) const {
932958
auto AllUses = MRI->use_nodbg_operands(MI.getOperand(0).getReg());
933-
bool ShouldSwap = false;
959+
unsigned Swap = 0, SwapNot = 0;
934960

935961
for (auto &Use : AllUses) {
936962
MachineInstr *UseInst = Use.getParent();
937963
if (UseInst->getOpcode() != AMDGPU::V_CNDMASK_B32_e64)
938964
return false;
965+
966+
UsesToProcess.push_back(&Use);
967+
939968
MachineOperand &Src0 = UseInst->getOperand(2);
940969
MachineOperand &Src1 = UseInst->getOperand(4);
941970

942971
bool Src0Imm = Src0.isImm();
943972
bool Src1Imm = Src1.isImm();
944973

945974
if (!Src1Imm && Src0Imm)
946-
return false;
947-
948-
UsesToProcess.push_back(&Use);
949-
950-
if (Src1Imm && !Src0Imm && !UseInst->getOperand(1).getImm())
951-
ShouldSwap = true;
975+
SwapNot++;
976+
else if (Src1Imm && !Src0Imm &&
977+
UseInst->getOperand(1).getImm() == SISrcMods::NONE)
978+
Swap++;
952979
}
953-
return ShouldSwap;
980+
return (Swap > SwapNot);
954981
}
955982

956983
static void swapCndOperands(MachineInstr &MI) {

‎llvm/test/CodeGen/AMDGPU/extract-subvector.ll‎

Lines changed: 25 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -210,14 +210,14 @@ define <4 x i64> @extract_4xi64(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i1 %
210210
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
211211
; GCN-NEXT: s_waitcnt vmcnt(0)
212212
; GCN-NEXT: v_mov_b32_e32 v1, 0xffff8000
213-
; GCN-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[4:5]
214-
; GCN-NEXT: v_cndmask_b32_e64 v0, v1, -1, vcc
215-
; GCN-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[6:7]
216-
; GCN-NEXT: v_cndmask_b32_e64 v2, v1, -1, vcc
217-
; GCN-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[8:9]
218-
; GCN-NEXT: v_cndmask_b32_e64 v4, v1, -1, vcc
219-
; GCN-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[10:11]
220-
; GCN-NEXT: v_cndmask_b32_e64 v6, v1, -1, vcc
213+
; GCN-NEXT: v_cmp_le_i64_e32 vcc, 0, v[4:5]
214+
; GCN-NEXT: v_cndmask_b32_e32 v0, -1, v1, vcc
215+
; GCN-NEXT: v_cmp_le_i64_e32 vcc, 0, v[6:7]
216+
; GCN-NEXT: v_cndmask_b32_e32 v2, -1, v1, vcc
217+
; GCN-NEXT: v_cmp_le_i64_e32 vcc, 0, v[8:9]
218+
; GCN-NEXT: v_cndmask_b32_e32 v4, -1, v1, vcc
219+
; GCN-NEXT: v_cmp_le_i64_e32 vcc, 0, v[10:11]
220+
; GCN-NEXT: v_cndmask_b32_e32 v6, -1, v1, vcc
221221
; GCN-NEXT: v_mov_b32_e32 v1, -1
222222
; GCN-NEXT: v_mov_b32_e32 v3, -1
223223
; GCN-NEXT: v_mov_b32_e32 v5, -1
@@ -300,23 +300,23 @@ define <8 x i64> @extract_8xi64(ptr addrspace(1) %p0, ptr addrspace(1) %p1, i1 %
300300
; GCN-NEXT: .LBB3_4: ; %exit
301301
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
302302
; GCN-NEXT: v_mov_b32_e32 v1, 0xffff8000
303-
; GCN-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[6:7]
304-
; GCN-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[8:9]
305-
; GCN-NEXT: v_cmp_gt_i64_e64 s[6:7], 0, v[10:11]
306-
; GCN-NEXT: v_cmp_gt_i64_e64 s[8:9], 0, v[12:13]
307-
; GCN-NEXT: v_cmp_gt_i64_e64 s[10:11], 0, v[14:15]
308-
; GCN-NEXT: s_waitcnt vmcnt(0)
309-
; GCN-NEXT: v_cmp_gt_i64_e64 s[12:13], 0, v[16:17]
310-
; GCN-NEXT: v_cmp_gt_i64_e64 s[14:15], 0, v[18:19]
311-
; GCN-NEXT: v_cmp_gt_i64_e64 s[16:17], 0, v[4:5]
312-
; GCN-NEXT: v_cndmask_b32_e64 v0, v1, -1, s[16:17]
313-
; GCN-NEXT: v_cndmask_b32_e64 v2, v1, -1, vcc
314-
; GCN-NEXT: v_cndmask_b32_e64 v4, v1, -1, s[4:5]
315-
; GCN-NEXT: v_cndmask_b32_e64 v6, v1, -1, s[6:7]
316-
; GCN-NEXT: v_cndmask_b32_e64 v8, v1, -1, s[8:9]
317-
; GCN-NEXT: v_cndmask_b32_e64 v10, v1, -1, s[10:11]
318-
; GCN-NEXT: v_cndmask_b32_e64 v12, v1, -1, s[12:13]
319-
; GCN-NEXT: v_cndmask_b32_e64 v14, v1, -1, s[14:15]
303+
; GCN-NEXT: v_cmp_le_i64_e32 vcc, 0, v[6:7]
304+
; GCN-NEXT: v_cmp_le_i64_e64 s[4:5], 0, v[8:9]
305+
; GCN-NEXT: v_cmp_le_i64_e64 s[6:7], 0, v[10:11]
306+
; GCN-NEXT: v_cmp_le_i64_e64 s[8:9], 0, v[12:13]
307+
; GCN-NEXT: v_cmp_le_i64_e64 s[10:11], 0, v[14:15]
308+
; GCN-NEXT: s_waitcnt vmcnt(0)
309+
; GCN-NEXT: v_cmp_le_i64_e64 s[12:13], 0, v[16:17]
310+
; GCN-NEXT: v_cmp_le_i64_e64 s[14:15], 0, v[18:19]
311+
; GCN-NEXT: v_cmp_le_i64_e64 s[16:17], 0, v[4:5]
312+
; GCN-NEXT: v_cndmask_b32_e64 v0, -1, v1, s[16:17]
313+
; GCN-NEXT: v_cndmask_b32_e32 v2, -1, v1, vcc
314+
; GCN-NEXT: v_cndmask_b32_e64 v4, -1, v1, s[4:5]
315+
; GCN-NEXT: v_cndmask_b32_e64 v6, -1, v1, s[6:7]
316+
; GCN-NEXT: v_cndmask_b32_e64 v8, -1, v1, s[8:9]
317+
; GCN-NEXT: v_cndmask_b32_e64 v10, -1, v1, s[10:11]
318+
; GCN-NEXT: v_cndmask_b32_e64 v12, -1, v1, s[12:13]
319+
; GCN-NEXT: v_cndmask_b32_e64 v14, -1, v1, s[14:15]
320320
; GCN-NEXT: v_mov_b32_e32 v1, -1
321321
; GCN-NEXT: v_mov_b32_e32 v3, -1
322322
; GCN-NEXT: v_mov_b32_e32 v5, -1

‎llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -88,9 +88,9 @@ define amdgpu_kernel void @v_round_f64(ptr addrspace(1) %out, ptr addrspace(1) %
8888
; SI-NEXT: v_not_b32_e32 v4, v4
8989
; SI-NEXT: v_and_b32_e32 v5, v3, v5
9090
; SI-NEXT: v_and_b32_e32 v4, v2, v4
91-
; SI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v6
92-
; SI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
93-
; SI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
91+
; SI-NEXT: v_cmp_le_i32_e32 vcc, 0, v6
92+
; SI-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc
93+
; SI-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
9494
; SI-NEXT: v_cmp_lt_i32_e32 vcc, 51, v6
9595
; SI-NEXT: v_cndmask_b32_e32 v5, v5, v3, vcc
9696
; SI-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc

‎llvm/test/CodeGen/AMDGPU/shrink-cndmask.ll‎

Lines changed: 146 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,149 @@
22
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s -check-prefix=GCN
33
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -check-prefix=GCN
44

5+
;tests for integer 32
6+
define amdgpu_cs void @test_i32_sge(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %out) {
7+
; GCN-LABEL: test_i32_sge:
8+
; GCN: ; %bb.0: ; %.entry
9+
; GCN-NEXT: v_cmp_lt_i32_e32 vcc_lo, 1, v0
10+
; GCN-NEXT: v_dual_cndmask_b32 v0, 0, v1 :: v_dual_cndmask_b32 v1, 0, v2
11+
; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
12+
; GCN-NEXT: s_endpgm
13+
.entry:
14+
%vcc = icmp sge i32 %a, 2
15+
%val1 = select i1 %vcc, i32 %p, i32 0
16+
%val2 = select i1 %vcc, i32 %q, i32 0
17+
%ret0 = insertelement <2 x i32> poison, i32 %val1, i32 0
18+
%ret1 = insertelement <2 x i32> %ret0, i32 %val2, i32 1
19+
store <2 x i32> %ret1, ptr addrspace(1) %out
20+
ret void
21+
}
22+
23+
define amdgpu_cs void @test_i32_sle(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %out) {
24+
; GCN-LABEL: test_i32_sle:
25+
; GCN: ; %bb.0: ; %.entry
26+
; GCN-NEXT: v_cmp_gt_i32_e32 vcc_lo, 3, v0
27+
; GCN-NEXT: v_dual_cndmask_b32 v0, 0, v1 :: v_dual_cndmask_b32 v1, 0, v2
28+
; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
29+
; GCN-NEXT: s_endpgm
30+
.entry:
31+
%vcc = icmp sle i32 %a, 2
32+
%val1 = select i1 %vcc, i32 %p, i32 0
33+
%val2 = select i1 %vcc, i32 %q, i32 0
34+
%ret0 = insertelement <2 x i32> poison, i32 %val1, i32 0
35+
%ret1 = insertelement <2 x i32> %ret0, i32 %val2, i32 1
36+
store <2 x i32> %ret1, ptr addrspace(1) %out
37+
ret void
38+
}
39+
40+
define amdgpu_cs void @test_i32_sgt(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %out) {
41+
; GCN-LABEL: test_i32_sgt:
42+
; GCN: ; %bb.0: ; %.entry
43+
; GCN-NEXT: v_cmp_le_i32_e32 vcc_lo, 2, v0
44+
; GCN-NEXT: v_dual_cndmask_b32 v0, 0, v1 :: v_dual_cndmask_b32 v1, 0, v2
45+
; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
46+
; GCN-NEXT: s_endpgm
47+
.entry:
48+
%vcc = icmp sgt i32 2, %a
49+
%val1 = select i1 %vcc, i32 0, i32 %p
50+
%val2 = select i1 %vcc, i32 0, i32 %q
51+
%ret0 = insertelement <2 x i32> poison, i32 %val1, i32 0
52+
%ret1 = insertelement <2 x i32> %ret0, i32 %val2, i32 1
53+
store <2 x i32> %ret1, ptr addrspace(1) %out
54+
ret void
55+
}
56+
57+
define amdgpu_cs void @test_i32_slt(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %out) {
58+
; GCN-LABEL: test_i32_slt:
59+
; GCN: ; %bb.0: ; %.entry
60+
; GCN-NEXT: v_cmp_ge_i32_e32 vcc_lo, 2, v0
61+
; GCN-NEXT: v_dual_cndmask_b32 v0, 0, v1 :: v_dual_cndmask_b32 v1, 0, v2
62+
; GCN-NEXT: global_store_b64 v[3:4], v[0:1], off
63+
; GCN-NEXT: s_endpgm
64+
.entry:
65+
%vcc = icmp slt i32 2, %a
66+
%val1 = select i1 %vcc, i32 0, i32 %p
67+
%val2 = select i1 %vcc, i32 0, i32 %q
68+
%ret0 = insertelement <2 x i32> poison, i32 %val1, i32 0
69+
%ret1 = insertelement <2 x i32> %ret0, i32 %val2, i32 1
70+
store <2 x i32> %ret1, ptr addrspace(1) %out
71+
ret void
72+
}
73+
74+
;tests for integer 64
75+
define amdgpu_cs void @test_i64_sge(i64 %a, i64 %p, i64 %q, ptr addrspace(1) %out) {
76+
; GCN-LABEL: test_i64_sge:
77+
; GCN: ; %bb.0: ; %.entry
78+
; GCN-NEXT: v_cmp_lt_i64_e32 vcc_lo, 1, v[0:1]
79+
; GCN-NEXT: v_dual_cndmask_b32 v1, 0, v3 :: v_dual_cndmask_b32 v0, 0, v2
80+
; GCN-NEXT: v_dual_cndmask_b32 v3, 0, v5 :: v_dual_cndmask_b32 v2, 0, v4
81+
; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
82+
; GCN-NEXT: s_endpgm
83+
.entry:
84+
%vcc = icmp sge i64 %a, 2
85+
%val1 = select i1 %vcc, i64 %p, i64 0
86+
%val2 = select i1 %vcc, i64 %q, i64 0
87+
%ret0 = insertelement <2 x i64> poison, i64 %val1, i64 0
88+
%ret1 = insertelement <2 x i64> %ret0, i64 %val2, i64 1
89+
store <2 x i64> %ret1, ptr addrspace(1) %out
90+
ret void
91+
}
92+
93+
define amdgpu_cs void @test_i64_sle(i64 %a, i64 %p, i64 %q, ptr addrspace(1) %out) {
94+
; GCN-LABEL: test_i64_sle:
95+
; GCN: ; %bb.0: ; %.entry
96+
; GCN-NEXT: v_cmp_gt_i64_e32 vcc_lo, 3, v[0:1]
97+
; GCN-NEXT: v_dual_cndmask_b32 v1, 0, v3 :: v_dual_cndmask_b32 v0, 0, v2
98+
; GCN-NEXT: v_dual_cndmask_b32 v3, 0, v5 :: v_dual_cndmask_b32 v2, 0, v4
99+
; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
100+
; GCN-NEXT: s_endpgm
101+
.entry:
102+
%vcc = icmp sle i64 %a, 2
103+
%val1 = select i1 %vcc, i64 %p, i64 0
104+
%val2 = select i1 %vcc, i64 %q, i64 0
105+
%ret0 = insertelement <2 x i64> poison, i64 %val1, i64 0
106+
%ret1 = insertelement <2 x i64> %ret0, i64 %val2, i64 1
107+
store <2 x i64> %ret1, ptr addrspace(1) %out
108+
ret void
109+
}
110+
111+
define amdgpu_cs void @test_i64_sgt(i64 %a, i64 %p, i64 %q, ptr addrspace(1) %out) {
112+
; GCN-LABEL: test_i64_sgt:
113+
; GCN: ; %bb.0: ; %.entry
114+
; GCN-NEXT: v_cmp_le_i64_e32 vcc_lo, 2, v[0:1]
115+
; GCN-NEXT: v_dual_cndmask_b32 v1, 0, v3 :: v_dual_cndmask_b32 v0, 0, v2
116+
; GCN-NEXT: v_dual_cndmask_b32 v3, 0, v5 :: v_dual_cndmask_b32 v2, 0, v4
117+
; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
118+
; GCN-NEXT: s_endpgm
119+
.entry:
120+
%vcc = icmp sgt i64 2, %a
121+
%val1 = select i1 %vcc, i64 0, i64 %p
122+
%val2 = select i1 %vcc, i64 0, i64 %q
123+
%ret0 = insertelement <2 x i64> poison, i64 %val1, i64 0
124+
%ret1 = insertelement <2 x i64> %ret0, i64 %val2, i64 1
125+
store <2 x i64> %ret1, ptr addrspace(1) %out
126+
ret void
127+
}
128+
129+
define amdgpu_cs void @test_i64_slt(i64 %a, i64 %p, i64 %q, ptr addrspace(1) %out) {
130+
; GCN-LABEL: test_i64_slt:
131+
; GCN: ; %bb.0: ; %.entry
132+
; GCN-NEXT: v_cmp_ge_i64_e32 vcc_lo, 2, v[0:1]
133+
; GCN-NEXT: v_dual_cndmask_b32 v1, 0, v3 :: v_dual_cndmask_b32 v0, 0, v2
134+
; GCN-NEXT: v_dual_cndmask_b32 v3, 0, v5 :: v_dual_cndmask_b32 v2, 0, v4
135+
; GCN-NEXT: global_store_b128 v[6:7], v[0:3], off
136+
; GCN-NEXT: s_endpgm
137+
.entry:
138+
%vcc = icmp slt i64 2, %a
139+
%val1 = select i1 %vcc, i64 0, i64 %p
140+
%val2 = select i1 %vcc, i64 0, i64 %q
141+
%ret0 = insertelement <2 x i64> poison, i64 %val1, i64 0
142+
%ret1 = insertelement <2 x i64> %ret0, i64 %val2, i64 1
143+
store <2 x i64> %ret1, ptr addrspace(1) %out
144+
ret void
145+
}
146+
147+
;tests for unsigned 32
5148
define amdgpu_cs void @test_u32_eq(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %out) {
6149
; GCN-LABEL: test_u32_eq:
7150
; GCN: ; %bb.0: ; %.entry
@@ -104,6 +247,7 @@ define amdgpu_cs void @test_u32_ult(i32 %a, i32 %p, i32 %q, ptr addrspace(1) %ou
104247
ret void
105248
}
106249

250+
;tests for unsigned 64
107251
define amdgpu_cs void @test_u64_eq(i64 %a, i64 %p, i64 %q, ptr addrspace(1) %out) {
108252
; GCN-LABEL: test_u64_eq:
109253
; GCN: ; %bb.0: ; %.entry
@@ -212,6 +356,7 @@ define amdgpu_cs void @test_u64_ult(i64 %a, i64 %p, i64 %q, ptr addrspace(1) %ou
212356
ret void
213357
}
214358

359+
;tests for float 32
215360
define amdgpu_cs void @test_f32_oeq(float %a, float %p, float %q, ptr addrspace(1) %out) {
216361
; GCN-LABEL: test_f32_oeq:
217362
; GCN: ; %bb.0: ; %.entry
@@ -349,6 +494,7 @@ define amdgpu_cs void @test_f32_olt(float %a, float %p, float %q, ptr addrspace(
349494
ret void
350495
}
351496

497+
;tests for float64
352498
define amdgpu_cs void @test_f64_oeq(double %a, double %p, double %q, ptr addrspace(1) %out) {
353499
; GCN-LABEL: test_f64_oeq:
354500
; GCN: ; %bb.0: ; %.entry

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