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| 1 | +//===-- RISCVInstrInfoZclsd.td -----------------------------*- tablegen -*-===// |
| 2 | +// |
| 3 | +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | +// See https://llvm.org/LICENSE.txt for license information. |
| 5 | +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | +// |
| 7 | +//===----------------------------------------------------------------------===// |
| 8 | +// |
| 9 | +// This file describes the RISC-V instructions from the standard 'Zclsd', |
| 10 | +// Compressed Load/Store pair instructions extension. |
| 11 | +// |
| 12 | +//===----------------------------------------------------------------------===// |
| 13 | + |
| 14 | +//===----------------------------------------------------------------------===// |
| 15 | +// Instruction Class Templates |
| 16 | +//===----------------------------------------------------------------------===// |
| 17 | + |
| 18 | +def GPRPairNoX0RV32Operand : AsmOperandClass { |
| 19 | + let Name = "GPRPairNoX0RV32"; |
| 20 | + let ParserMethod = "parseGPRPair<false>"; |
| 21 | + let PredicateMethod = "isGPRPairNoX0"; |
| 22 | + let RenderMethod = "addRegOperands"; |
| 23 | +} |
| 24 | + |
| 25 | +def GPRPairNoX0RV32 : RegisterOperand<GPRPairNoX0> { |
| 26 | + let ParserMatchClass = GPRPairNoX0RV32Operand; |
| 27 | +} |
| 28 | + |
| 29 | +def GPRPairCRV32Operand : AsmOperandClass { |
| 30 | + let Name = "GPRPairCRV32"; |
| 31 | + let ParserMethod = "parseGPRPair<false>"; |
| 32 | + let PredicateMethod = "isGPRPairC"; |
| 33 | + let RenderMethod = "addRegOperands"; |
| 34 | +} |
| 35 | + |
| 36 | +def GPRPairCRV32 : RegisterOperand<GPRPairC> { |
| 37 | + let ParserMatchClass = GPRPairCRV32Operand; |
| 38 | +} |
| 39 | + |
| 40 | +let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in |
| 41 | +class PairCStackLoad<bits<3> funct3, string OpcodeStr, |
| 42 | + DAGOperand RC, DAGOperand opnd> |
| 43 | + : RVInst16CI<funct3, 0b10, (outs RC:$rd), (ins SPMem:$rs1, opnd:$imm), |
| 44 | + OpcodeStr, "$rd, ${imm}(${rs1})">; |
| 45 | + |
| 46 | +let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in |
| 47 | +class PairCStackStore<bits<3> funct3, string OpcodeStr, |
| 48 | + DAGOperand RC, DAGOperand opnd> |
| 49 | + : RVInst16CSS<funct3, 0b10, (outs), (ins RC:$rs2, SPMem:$rs1, opnd:$imm), |
| 50 | + OpcodeStr, "$rs2, ${imm}(${rs1})">; |
| 51 | + |
| 52 | +let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in |
| 53 | +class PairCLoad_ri<bits<3> funct3, string OpcodeStr, |
| 54 | + DAGOperand RC, DAGOperand opnd> |
| 55 | + : RVInst16CL<funct3, 0b00, (outs RC:$rd), (ins GPRCMem:$rs1, opnd:$imm), |
| 56 | + OpcodeStr, "$rd, ${imm}(${rs1})">; |
| 57 | + |
| 58 | +let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in |
| 59 | +class PairCStore_rri<bits<3> funct3, string OpcodeStr, |
| 60 | + DAGOperand RC, DAGOperand opnd> |
| 61 | + : RVInst16CS<funct3, 0b00, (outs), (ins RC:$rs2,GPRCMem:$rs1, opnd:$imm), |
| 62 | + OpcodeStr, "$rs2, ${imm}(${rs1})">; |
| 63 | + |
| 64 | +//===----------------------------------------------------------------------===// |
| 65 | +// Instructions |
| 66 | +//===----------------------------------------------------------------------===// |
| 67 | + |
| 68 | +let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in { |
| 69 | +def C_LDSP_RV32 : PairCStackLoad<0b011, "c.ldsp", GPRPairNoX0RV32, uimm9_lsb000>, |
| 70 | + Sched<[WriteLDD, ReadMemBase]> { |
| 71 | + let Inst{4-2} = imm{8-6}; |
| 72 | +} |
| 73 | + |
| 74 | +def C_SDSP_RV32 : PairCStackStore<0b111, "c.sdsp", GPRPairRV32, uimm9_lsb000>, |
| 75 | + Sched<[WriteSTD, ReadStoreData, ReadMemBase]> { |
| 76 | + let Inst{9-7} = imm{8-6}; |
| 77 | +} |
| 78 | + |
| 79 | +def C_LD_RV32 : PairCLoad_ri<0b011, "c.ld", GPRPairCRV32, uimm8_lsb000>, |
| 80 | + Sched<[WriteLDD, ReadMemBase]> { |
| 81 | + bits<8> imm; |
| 82 | + let Inst{12-10} = imm{5-3}; |
| 83 | + let Inst{6-5} = imm{7-6}; |
| 84 | +} |
| 85 | + |
| 86 | +def C_SD_RV32 : PairCStore_rri<0b111, "c.sd", GPRPairCRV32, uimm8_lsb000>, |
| 87 | + Sched<[WriteSTD, ReadStoreData, ReadMemBase]> { |
| 88 | + bits<8> imm; |
| 89 | + let Inst{12-10} = imm{5-3}; |
| 90 | + let Inst{6-5} = imm{7-6}; |
| 91 | +} |
| 92 | +}// Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" |
| 93 | + |
| 94 | +//===----------------------------------------------------------------------===// |
| 95 | +// Compress Instruction tablegen backend. |
| 96 | +//===----------------------------------------------------------------------===// |
| 97 | + |
| 98 | +let Predicates = [HasStdExtZclsd, IsRV32] in { |
| 99 | +def : CompressPat<(LD_RV32 GPRPairNoX0RV32:$rd, SPMem:$rs1, uimm9_lsb000:$imm), |
| 100 | + (C_LDSP_RV32 GPRPairNoX0RV32:$rd, SPMem:$rs1, uimm9_lsb000:$imm)>; |
| 101 | +def : CompressPat<(SD_RV32 GPRPairRV32:$rs2, SPMem:$rs1, uimm9_lsb000:$imm), |
| 102 | + (C_SDSP_RV32 GPRPairRV32:$rs2, SPMem:$rs1, uimm9_lsb000:$imm)>; |
| 103 | +def : CompressPat<(LD_RV32 GPRPairCRV32:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm), |
| 104 | + (C_LD_RV32 GPRPairCRV32:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm)>; |
| 105 | +def : CompressPat<(SD_RV32 GPRPairCRV32:$rs2, GPRCMem:$rs1, uimm8_lsb000:$imm), |
| 106 | + (C_SD_RV32 GPRPairCRV32:$rs2, GPRCMem:$rs1, uimm8_lsb000:$imm)>; |
| 107 | +} // Predicates = [HasStdExtZclsd, IsRV32] |
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