Simplify code

LU-JOHN · LU-JOHN · commit 482f3939babe · 2025-06-16T08:57:14.000-05:00
Signed-off-by: John Lu &lt;John.Lu@amd.com&gt;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -4239,10 +4239,7 @@ SDValue AMDGPUTargetLowering::performSraCombine(SDNode *N,
     }
     Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, ConcatType, HiAndLoOps);
   } else {
-    if (Known.getMinValue().getZExtValue() == (ElementType.getSizeInBits() - 1))
-      Vec = DAG.getBuildVector(ConcatType, SL, {HiShift, HiShift});
-    else
-      Vec = DAG.getBuildVector(ConcatType, SL, {NewShift, HiShift});
+    Vec = DAG.getBuildVector(ConcatType, SL, {NewShift, HiShift});
   }
   return DAG.getNode(ISD::BITCAST, SL, VT, Vec);
 }

Original file line number	Diff line number	Diff line change
`@@ -4239,10 +4239,7 @@ SDValue AMDGPUTargetLowering::performSraCombine(SDNode *N,`
`4239`	`4239`	`}`
`4240`	`4240`	`Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, ConcatType, HiAndLoOps);`
`4241`	`4241`	`} else {`
`4242`		`- if (Known.getMinValue().getZExtValue() == (ElementType.getSizeInBits() - 1))`
`4243`		`- Vec = DAG.getBuildVector(ConcatType, SL, {HiShift, HiShift});`
`4244`		`- else`
`4245`		`- Vec = DAG.getBuildVector(ConcatType, SL, {NewShift, HiShift});`
	`4242`	`+ Vec = DAG.getBuildVector(ConcatType, SL, {NewShift, HiShift});`
`4246`	`4243`	`}`
`4247`	`4244`	`return DAG.getNode(ISD::BITCAST, SL, VT, Vec);`
`4248`	`4245`	`}`