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[llvm-mca][FeatureRequest] Itimeline graph, note source of delay for each instruction #123756 
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‎llvm/test/tools/llvm-mca/AArch64/Cortex/A510-writeback.s‎

Lines changed: 728 additions & 91 deletions
Large diffs are not rendered by default.

‎llvm/test/tools/llvm-mca/AArch64/Cortex/A53-carry-over.s‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -58,7 +58,14 @@ add w19, w20, w21
5858
# CHECK-NEXT: 1.00 - - - - - - - add w19, w20, w21
5959

6060
# CHECK: Timeline view:
61-
# CHECK-NEXT: Index 01234567
61+
# CHECK-NEXT: D: Instruction Dispatched
62+
# CHECK-NEXT: e: Instruction Executingn
63+
# CHECK-NEXT: E: Instruction Executed (write-back stage)
64+
# CHECK-NEXT: p: Instruction waiting for data dependency
65+
# CHECK-NEXT: =: Instruction waiting for available HW resource
66+
# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
67+
68+
# CHECK: Index 01234567
6269

6370
# CHECK: [0,0] DeeeE. . ldp w3, w5, [x10], #4
6471
# CHECK-NEXT: [0,1] .DeeE. . add w10, w11, w12

‎llvm/test/tools/llvm-mca/AArch64/Cortex/A53-writeback.s‎

Lines changed: 728 additions & 91 deletions
Large diffs are not rendered by default.

‎llvm/test/tools/llvm-mca/AArch64/Cortex/A55-add-sequence.s‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,14 @@ add w1, w0, #4
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# CHECK-NEXT: 1.00 - - - - - - - - - - - add w1, w0, #4
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5858
# CHECK: Timeline view:
59-
# CHECK-NEXT: Index 012345678
59+
# CHECK-NEXT: D: Instruction Dispatched
60+
# CHECK-NEXT: e: Instruction Executingn
61+
# CHECK-NEXT: E: Instruction Executed (write-back stage)
62+
# CHECK-NEXT: p: Instruction waiting for data dependency
63+
# CHECK-NEXT: =: Instruction waiting for available HW resource
64+
# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
65+
66+
# CHECK: Index 012345678
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6168
# CHECK: [0,0] DeeE . . add w2, w3, #1
6269
# CHECK-NEXT: [0,1] DeeE . . add w4, w3, #2, lsl #12

‎llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-views.s‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -90,7 +90,14 @@ str w0, [x21, x18, lsl #2]
9090
# CHECK-NEXT: - - - - - - - - - - - 1.00 str w0, [x21, x18, lsl #2]
9191

9292
# CHECK: Timeline view:
93-
# CHECK-NEXT: 0123456
93+
# CHECK-NEXT: D: Instruction Dispatched
94+
# CHECK-NEXT: e: Instruction Executingn
95+
# CHECK-NEXT: E: Instruction Executed (write-back stage)
96+
# CHECK-NEXT: p: Instruction waiting for data dependency
97+
# CHECK-NEXT: =: Instruction waiting for available HW resource
98+
# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
99+
100+
# CHECK: 0123456
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# CHECK-NEXT: Index 0123456789
95102

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# CHECK: [0,0] DeeE . . .. ldr w4, [x2], #4

‎llvm/test/tools/llvm-mca/AArch64/Cortex/A55-in-order-retire.s‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -90,7 +90,14 @@ add w7, w9, w0
9090
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - add w7, w9, w0
9191

9292
# CHECK: Timeline view:
93-
# CHECK-NEXT: 012345678
93+
# CHECK-NEXT: D: Instruction Dispatched
94+
# CHECK-NEXT: e: Instruction Executingn
95+
# CHECK-NEXT: E: Instruction Executed (write-back stage)
96+
# CHECK-NEXT: p: Instruction waiting for data dependency
97+
# CHECK-NEXT: =: Instruction waiting for available HW resource
98+
# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
99+
100+
# CHECK: 012345678
94101
# CHECK-NEXT: Index 0123456789
95102

96103
# CHECK: [0,0] DeeeeeeeE . . . sdiv w12, w21, w0

‎llvm/test/tools/llvm-mca/AArch64/Cortex/A55-load-readadv.s‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -509,7 +509,14 @@ ldpsw x0, x1, [x2], #16
509509
# CHECK-NEXT: - - - - - - - - - 1.00 - - ldpsw x0, x1, [x2], #16
510510

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# CHECK: Timeline view:
512-
# CHECK-NEXT: 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789
512+
# CHECK-NEXT: D: Instruction Dispatched
513+
# CHECK-NEXT: e: Instruction Executingn
514+
# CHECK-NEXT: E: Instruction Executed (write-back stage)
515+
# CHECK-NEXT: p: Instruction waiting for data dependency
516+
# CHECK-NEXT: =: Instruction waiting for available HW resource
517+
# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
518+
519+
# CHECK: 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789
513520
# CHECK-NEXT: Index 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 0123456789 012345
514521

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# CHECK: [0,0] DeeE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . add x2, x3, #1

‎llvm/test/tools/llvm-mca/AArch64/Cortex/A55-load-store-alias.s‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,14 @@ ldr x3, [x10]
6464
# CHECK-NEXT: - - - - - - - - - 1.00 - - ldr x3, [x10]
6565

6666
# CHECK: Timeline view:
67-
# CHECK-NEXT: 0123456789 0
67+
# CHECK-NEXT: D: Instruction Dispatched
68+
# CHECK-NEXT: e: Instruction Executingn
69+
# CHECK-NEXT: E: Instruction Executed (write-back stage)
70+
# CHECK-NEXT: p: Instruction waiting for data dependency
71+
# CHECK-NEXT: =: Instruction waiting for available HW resource
72+
# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
73+
74+
# CHECK: 0123456789 0
6875
# CHECK-NEXT: Index 0123456789 0123456789
6976

7077
# CHECK: [0,0] DE . . . . . . str x1, [x10]

‎llvm/test/tools/llvm-mca/AArch64/Cortex/A55-load-store-noalias.s‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -62,7 +62,14 @@ ldr x3, [x10]
6262
# CHECK-NEXT: - - - - - - - - - 1.00 - - ldr x3, [x10]
6363

6464
# CHECK: Timeline view:
65-
# CHECK-NEXT: 012345
65+
# CHECK-NEXT: D: Instruction Dispatched
66+
# CHECK-NEXT: e: Instruction Executingn
67+
# CHECK-NEXT: E: Instruction Executed (write-back stage)
68+
# CHECK-NEXT: p: Instruction waiting for data dependency
69+
# CHECK-NEXT: =: Instruction waiting for available HW resource
70+
# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
71+
72+
# CHECK: 012345
6673
# CHECK-NEXT: Index 0123456789
6774

6875
# CHECK: [0,0] DE . . . str x1, [x10]

‎llvm/test/tools/llvm-mca/AArch64/Cortex/A55-out-of-order-retire.s‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -88,7 +88,14 @@ add w7, w9, w0
8888
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - add w7, w9, w0
8989

9090
# CHECK: Timeline view:
91-
# CHECK-NEXT: 0123456789
91+
# CHECK-NEXT: D: Instruction Dispatched
92+
# CHECK-NEXT: e: Instruction Executingn
93+
# CHECK-NEXT: E: Instruction Executed (write-back stage)
94+
# CHECK-NEXT: p: Instruction waiting for data dependency
95+
# CHECK-NEXT: =: Instruction waiting for available HW resource
96+
# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
97+
98+
# CHECK: 0123456789
9299
# CHECK-NEXT: Index 0123456789 0123
93100

94101
# CHECK: [0,0] DeeeeeeeeeeeeE . . . fdiv s1, s2, s3

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