Widen 128/256 bit vector types when AVX512VL is not available.

KavinTheG · KavinTheG · commit 484cea4f06e5 · 2025-11-11T21:33:56.000-05:00
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -1829,6 +1829,16 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
       setOperationAction(ISD::FCOPYSIGN, VT, Custom);
       setOperationAction(ISD::FCANONICALIZE, VT, Custom);
     }
+
+    for (MVT VT : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64, MVT::v8f32,
+                   MVT::v4f64, MVT::v16f32, MVT::v8f64})
+      setOperationAction(ISD::FLDEXP, VT, Custom);
+
+    if (Subtarget.hasFP16()) {
+      for (MVT VT : {MVT::f16, MVT::v8f16, MVT::v16f16, MVT::v32f16})
+        setOperationAction(ISD::FLDEXP, VT, Custom);
+    }
+
     setOperationAction(ISD::LRINT, MVT::v16f32,
                        Subtarget.hasDQI() ? Legal : Custom);
     setOperationAction(ISD::LRINT, MVT::v8f64,
@@ -2591,26 +2601,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
     setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i128, Custom);
   }
 
-  if (Subtarget.hasAVX512()) {
-    for (MVT VT : { MVT::f32, MVT::f64, MVT::v16f32, MVT::v8f64})
-      setOperationAction(ISD::FLDEXP, VT, Custom);
-    
-    if (Subtarget.hasVLX()) {
-      for (MVT VT : { MVT::v4f32, MVT::v2f64, MVT::v8f32, MVT::v4f64 }) 
-        setOperationAction(ISD::FLDEXP, VT, Custom);
-
-      if (Subtarget.hasFP16()) {
-        for (MVT VT : { MVT::v8f16, MVT::v16f16, MVT::v32f16 })
-          setOperationAction(ISD::FLDEXP, VT, Custom);
-      }
-    }
-    
-    if (Subtarget.hasFP16()) {
-      for (MVT VT : { MVT::f16, MVT::v32f16 })
-        setOperationAction(ISD::FLDEXP, VT, Custom);
-    }
-  }
-
   // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
   // is. We should promote the value to 64-bits to solve this.
   // This is what the CRT headers do - `fmodf` is an inline header
@@ -19177,48 +19167,67 @@ static SDValue LowerFLDEXP(SDValue Op, const X86Subtarget &Subtarget,
   SDValue Exp = Op.getOperand(1);
   MVT XVT, ExpVT; 
 
-  switch (XTy.SimpleTy) { 
-    default:
-      return SDValue();
-    case MVT::f16:
-      if (Subtarget.hasFP16()) {
-        XVT = Subtarget.hasVLX() ? MVT::v8f16 : MVT::v32f16;
-        ExpVT = XVT;
-        break;
-      } 
-      X = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, X);
-      [[fallthrough]];
-    case MVT::f32:
-      XVT = MVT::v4f32;
-      ExpVT = MVT::v4f32;
+  switch (XTy.SimpleTy) {
+  default:
+    return SDValue();
+  case MVT::f16:
+    if (Subtarget.hasFP16()) {
+      XVT = MVT::v8f16;
+      ExpVT = XVT;
+      break;
+    }
+    X = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, X);
+    [[fallthrough]];
+  case MVT::f32:
+    XVT = MVT::v4f32;
+    ExpVT = MVT::v4f32;
+    break;
+  case MVT::f64:
+    XVT = MVT::v2f64;
+    ExpVT = MVT::v2f64;
+    break;
+  case MVT::v4f32:
+  case MVT::v2f64:
+    if (!Subtarget.hasVLX()) {
+      XVT = XTy == MVT::v4f32 ? MVT::v16f32 : MVT::v8f64;
+      ExpVT = XVT;
       break;
-    case MVT::f64:
-      XVT = MVT::v2f64;
-      ExpVT = MVT::v2f64;
+    }
+    [[fallthrough]];
+  case MVT::v8f32:
+  case MVT::v4f64:
+    if (!Subtarget.hasVLX()) {
+      XVT = XTy == MVT::v8f32 ? MVT::v16f32 : MVT::v8f64;
+      ExpVT = XVT;
       break;
-    case MVT::v4f32:
-    case MVT::v2f64:
-    case MVT::v8f32:
-    case MVT::v4f64:
-    case MVT::v16f32:
-    case MVT::v8f64:
-      Exp = DAG.getNode(ISD::SINT_TO_FP, DL, XTy, Exp); 
-      return DAG.getNode(X86ISD::SCALEF, DL, XTy, X, Exp, X);
+    }
+    [[fallthrough]];
+  case MVT::v16f32:
+  case MVT::v8f64:
+    Exp = DAG.getNode(ISD::SINT_TO_FP, DL, XTy, Exp);
+    return DAG.getNode(X86ISD::SCALEF, DL, XTy, X, Exp, X);
   }
 
-  SDValue Zero = DAG.getConstant(0, DL, MVT::i64);
   Exp = DAG.getNode(ISD::SINT_TO_FP, DL, X.getValueType(), Exp);
-  SDValue VX =
-      DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, XVT, DAG.getUNDEF(XVT), X, Zero);
-  SDValue VExp = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ExpVT,
-                             DAG.getUNDEF(ExpVT), Exp, Zero);
-  SDValue Scalef = DAG.getNode(X86ISD::SCALEFS, DL, XVT, VX, VExp, VX);
-  SDValue Final =
-      DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, X.getValueType(), Scalef, Zero);
-  if (X.getValueType() != XTy)
-    Final = DAG.getNode(ISD::FP_ROUND, DL, XTy, Final,
-                        DAG.getIntPtrConstant(1, SDLoc(Op)));
-  return Final;
+  if (XTy.isVector()) {
+    SDValue WideX =
+        DAG.getInsertSubvector(DL, DAG.getUNDEF(XVT), X, 0);
+    SDValue WideExp =
+        DAG.getInsertSubvector(DL, DAG.getUNDEF(ExpVT), Exp, 0);
+    SDValue Scalef =
+        DAG.getNode(X86ISD::SCALEF, DL, XVT, WideX, WideExp, WideX);
+    SDValue Final = DAG.getExtractSubvector(DL, XTy, Scalef, 0);
+    return Final;
+  } else {
+    SDValue VX = DAG.getInsertVectorElt(DL, DAG.getUNDEF(XVT), X, 0);
+    SDValue VExp = DAG.getInsertVectorElt(DL, DAG.getUNDEF(ExpVT), Exp, 0);
+    SDValue Scalefs = DAG.getNode(X86ISD::SCALEFS, DL, XVT, VX, VExp, VX);
+    SDValue Final = DAG.getExtractVectorElt(DL, X.getValueType(), Scalefs, 0);
+    if (X.getValueType() != XTy)
+      Final = DAG.getNode(ISD::FP_ROUND, DL, XTy, Final,
+                          DAG.getIntPtrConstant(1, SDLoc(Op)));
+    return Final;
+  }
 }
 
 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, const X86Subtarget &Subtarget,
diff --git a/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll b/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
@@ -114,21 +114,11 @@ define <4 x float> @fmul_pow2_ldexp_4xfloat(<4 x i32> %i) {
 ;
 ; CHECK-ONLY-AVX512F-LABEL: fmul_pow2_ldexp_4xfloat:
 ; CHECK-ONLY-AVX512F:       # %bb.0:
-; CHECK-ONLY-AVX512F-NEXT:    vcvtdq2ps %xmm0, %xmm1
-; CHECK-ONLY-AVX512F-NEXT:    vmovss {{.*#+}} xmm2 = [9.0E+0,0.0E+0,0.0E+0,0.0E+0]
-; CHECK-ONLY-AVX512F-NEXT:    vscalefss %xmm1, %xmm2, %xmm1
-; CHECK-ONLY-AVX512F-NEXT:    vshufps {{.*#+}} xmm3 = xmm0[1,1,1,1]
-; CHECK-ONLY-AVX512F-NEXT:    vcvtdq2ps %xmm3, %xmm3
-; CHECK-ONLY-AVX512F-NEXT:    vscalefss %xmm3, %xmm2, %xmm3
-; CHECK-ONLY-AVX512F-NEXT:    vunpcklps {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1]
-; CHECK-ONLY-AVX512F-NEXT:    vshufps {{.*#+}} xmm3 = xmm0[2,3,2,3]
-; CHECK-ONLY-AVX512F-NEXT:    vcvtdq2ps %xmm3, %xmm3
-; CHECK-ONLY-AVX512F-NEXT:    vscalefss %xmm3, %xmm2, %xmm3
-; CHECK-ONLY-AVX512F-NEXT:    vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm3[0]
-; CHECK-ONLY-AVX512F-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
+; CHECK-ONLY-AVX512F-NEXT:    vbroadcastss {{.*#+}} xmm1 = [9.0E+0,9.0E+0,9.0E+0,9.0E+0]
 ; CHECK-ONLY-AVX512F-NEXT:    vcvtdq2ps %xmm0, %xmm0
-; CHECK-ONLY-AVX512F-NEXT:    vscalefss %xmm0, %xmm2, %xmm0
-; CHECK-ONLY-AVX512F-NEXT:    vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
+; CHECK-ONLY-AVX512F-NEXT:    vscalefps %zmm0, %zmm1, %zmm0
+; CHECK-ONLY-AVX512F-NEXT:    # kill: def $xmm0 killed $xmm0 killed $zmm0
+; CHECK-ONLY-AVX512F-NEXT:    vzeroupper
 ; CHECK-ONLY-AVX512F-NEXT:    retq
 ;
 ; CHECK-SKX-LABEL: fmul_pow2_ldexp_4xfloat:
diff --git a/llvm/test/CodeGen/X86/ldexp-avx512.ll b/llvm/test/CodeGen/X86/ldexp-avx512.ll
@@ -1,21 +1,37 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
-; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512f | FileCheck %s --check-prefixes=CHECK,AVX512
-; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512vl,+avx512fp16 | FileCheck %s --check-prefixes=CHECK,AVX512VL
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512f | FileCheck %s --check-prefixes=CHECK,AVX512,AVX512F
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512f,+avx512fp16 | FileCheck %s --check-prefixes=CHECK,AVX512,AVX512FP16
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512vl | FileCheck %s --check-prefixes=CHECK,AVX512VL,AVX512VLF
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512vl,+avx512fp16 | FileCheck %s --check-prefixes=CHECK,AVX512VLFP16
 
 define half @test_half(half %x, i32 %exp) nounwind {
-; AVX512-LABEL: test_half:
-; AVX512:       # %bb.0: # %entry
-; AVX512-NEXT:    vcvtsi2ss %edi, %xmm15, %xmm1
-; AVX512-NEXT:    vcvtph2ps %xmm0, %xmm0
-; AVX512-NEXT:    vscalefss %xmm1, %xmm0, %xmm0
-; AVX512-NEXT:    vcvtps2ph $4, %xmm0, %xmm0
-; AVX512-NEXT:    retq
+; AVX512F-LABEL: test_half:
+; AVX512F:       # %bb.0: # %entry
+; AVX512F-NEXT:    vcvtsi2ss %edi, %xmm15, %xmm1
+; AVX512F-NEXT:    vcvtph2ps %xmm0, %xmm0
+; AVX512F-NEXT:    vscalefss %xmm1, %xmm0, %xmm0
+; AVX512F-NEXT:    vcvtps2ph $4, %xmm0, %xmm0
+; AVX512F-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_half:
+; AVX512FP16:       # %bb.0: # %entry
+; AVX512FP16-NEXT:    vcvtsi2sh %edi, %xmm31, %xmm1
+; AVX512FP16-NEXT:    vscalefsh %xmm1, %xmm0, %xmm0
+; AVX512FP16-NEXT:    retq
 ;
 ; AVX512VL-LABEL: test_half:
 ; AVX512VL:       # %bb.0: # %entry
-; AVX512VL-NEXT:    vcvtsi2sh %edi, %xmm31, %xmm1
-; AVX512VL-NEXT:    vscalefsh %xmm1, %xmm0, %xmm0
+; AVX512VL-NEXT:    vcvtsi2ss %edi, %xmm15, %xmm1
+; AVX512VL-NEXT:    vcvtph2ps %xmm0, %xmm0
+; AVX512VL-NEXT:    vscalefss %xmm1, %xmm0, %xmm0
+; AVX512VL-NEXT:    vcvtps2ph $4, %xmm0, %xmm0
 ; AVX512VL-NEXT:    retq
+;
+; AVX512VLFP16-LABEL: test_half:
+; AVX512VLFP16:       # %bb.0: # %entry
+; AVX512VLFP16-NEXT:    vcvtsi2sh %edi, %xmm31, %xmm1
+; AVX512VLFP16-NEXT:    vscalefsh %xmm1, %xmm0, %xmm0
+; AVX512VLFP16-NEXT:    retq
 entry:
   %r = tail call fast half @llvm.ldexp.f16.i32(half %x, i32 %exp)
   ret half %r
@@ -240,30 +256,24 @@ declare <8 x half> @llvm.ldexp.v8f16.v8i16(<8 x half>, <8 x i16>)
 define <4 x float> @test_ldexp_4xfloat(<4 x float> %x, <4 x i32> %exp) nounwind {
 ; AVX512-LABEL: test_ldexp_4xfloat:
 ; AVX512:       # %bb.0:
-; AVX512-NEXT:    vcvtdq2ps %xmm1, %xmm2
-; AVX512-NEXT:    vscalefss %xmm2, %xmm0, %xmm2
-; AVX512-NEXT:    vmovshdup {{.*#+}} xmm3 = xmm0[1,1,3,3]
-; AVX512-NEXT:    vshufps {{.*#+}} xmm4 = xmm1[1,1,1,1]
-; AVX512-NEXT:    vcvtdq2ps %xmm4, %xmm4
-; AVX512-NEXT:    vscalefss %xmm4, %xmm3, %xmm3
-; AVX512-NEXT:    vunpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
-; AVX512-NEXT:    vshufpd {{.*#+}} xmm3 = xmm0[1,0]
-; AVX512-NEXT:    vshufps {{.*#+}} xmm4 = xmm1[2,3,2,3]
-; AVX512-NEXT:    vcvtdq2ps %xmm4, %xmm4
-; AVX512-NEXT:    vscalefss %xmm4, %xmm3, %xmm3
-; AVX512-NEXT:    vmovlhps {{.*#+}} xmm2 = xmm2[0],xmm3[0]
-; AVX512-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
-; AVX512-NEXT:    vshufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
+; AVX512-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
 ; AVX512-NEXT:    vcvtdq2ps %xmm1, %xmm1
-; AVX512-NEXT:    vscalefss %xmm1, %xmm0, %xmm0
-; AVX512-NEXT:    vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0]
+; AVX512-NEXT:    vscalefps %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    # kill: def $xmm0 killed $xmm0 killed $zmm0
+; AVX512-NEXT:    vzeroupper
 ; AVX512-NEXT:    retq
 ;
 ; AVX512VL-LABEL: test_ldexp_4xfloat:
 ; AVX512VL:       # %bb.0:
 ; AVX512VL-NEXT:    vcvtdq2ps %xmm1, %xmm1
 ; AVX512VL-NEXT:    vscalefps %xmm1, %xmm0, %xmm0
 ; AVX512VL-NEXT:    retq
+;
+; AVX512VLFP16-LABEL: test_ldexp_4xfloat:
+; AVX512VLFP16:       # %bb.0:
+; AVX512VLFP16-NEXT:    vcvtdq2ps %xmm1, %xmm1
+; AVX512VLFP16-NEXT:    vscalefps %xmm1, %xmm0, %xmm0
+; AVX512VLFP16-NEXT:    retq
   %r = call <4 x float> @llvm.ldexp.v4f32.v4i32(<4 x float> %x, <4 x i32> %exp)
   ret <4 x float> %r
 }
@@ -663,50 +673,23 @@ declare <16 x half> @llvm.ldexp.v16f16.v16i16(<16 x half>, <16 x i16>)
 define <8 x float> @test_ldexp_8xfloat(<8 x float> %x, <8 x i32> %exp) nounwind {
 ; AVX512-LABEL: test_ldexp_8xfloat:
 ; AVX512:       # %bb.0:
-; AVX512-NEXT:    vextractf128 $1, %ymm0, %xmm2
-; AVX512-NEXT:    vextractf128 $1, %ymm1, %xmm3
-; AVX512-NEXT:    vcvtdq2ps %xmm3, %xmm4
-; AVX512-NEXT:    vscalefss %xmm4, %xmm2, %xmm4
-; AVX512-NEXT:    vmovshdup {{.*#+}} xmm5 = xmm2[1,1,3,3]
-; AVX512-NEXT:    vshufps {{.*#+}} xmm6 = xmm3[1,1,1,1]
-; AVX512-NEXT:    vcvtdq2ps %xmm6, %xmm6
-; AVX512-NEXT:    vscalefss %xmm6, %xmm5, %xmm5
-; AVX512-NEXT:    vunpcklps {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
-; AVX512-NEXT:    vshufpd {{.*#+}} xmm5 = xmm2[1,0]
-; AVX512-NEXT:    vshufps {{.*#+}} xmm6 = xmm3[2,3,2,3]
-; AVX512-NEXT:    vcvtdq2ps %xmm6, %xmm6
-; AVX512-NEXT:    vscalefss %xmm6, %xmm5, %xmm5
-; AVX512-NEXT:    vmovlhps {{.*#+}} xmm4 = xmm4[0],xmm5[0]
-; AVX512-NEXT:    vshufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
-; AVX512-NEXT:    vshufps {{.*#+}} xmm3 = xmm3[3,3,3,3]
-; AVX512-NEXT:    vcvtdq2ps %xmm3, %xmm3
-; AVX512-NEXT:    vscalefss %xmm3, %xmm2, %xmm2
-; AVX512-NEXT:    vinsertps {{.*#+}} xmm2 = xmm4[0,1,2],xmm2[0]
-; AVX512-NEXT:    vcvtdq2ps %xmm1, %xmm3
-; AVX512-NEXT:    vscalefss %xmm3, %xmm0, %xmm3
-; AVX512-NEXT:    vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
-; AVX512-NEXT:    vshufps {{.*#+}} xmm5 = xmm1[1,1,1,1]
-; AVX512-NEXT:    vcvtdq2ps %xmm5, %xmm5
-; AVX512-NEXT:    vscalefss %xmm5, %xmm4, %xmm4
-; AVX512-NEXT:    vunpcklps {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1]
-; AVX512-NEXT:    vshufpd {{.*#+}} xmm4 = xmm0[1,0]
-; AVX512-NEXT:    vshufps {{.*#+}} xmm5 = xmm1[2,3,2,3]
-; AVX512-NEXT:    vcvtdq2ps %xmm5, %xmm5
-; AVX512-NEXT:    vscalefss %xmm5, %xmm4, %xmm4
-; AVX512-NEXT:    vmovlhps {{.*#+}} xmm3 = xmm3[0],xmm4[0]
-; AVX512-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
-; AVX512-NEXT:    vshufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
-; AVX512-NEXT:    vcvtdq2ps %xmm1, %xmm1
-; AVX512-NEXT:    vscalefss %xmm1, %xmm0, %xmm0
-; AVX512-NEXT:    vinsertps {{.*#+}} xmm0 = xmm3[0,1,2],xmm0[0]
-; AVX512-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX512-NEXT:    # kill: def $ymm0 killed $ymm0 def $zmm0
+; AVX512-NEXT:    vcvtdq2ps %ymm1, %ymm1
+; AVX512-NEXT:    vscalefps %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    # kill: def $ymm0 killed $ymm0 killed $zmm0
 ; AVX512-NEXT:    retq
 ;
 ; AVX512VL-LABEL: test_ldexp_8xfloat:
 ; AVX512VL:       # %bb.0:
 ; AVX512VL-NEXT:    vcvtdq2ps %ymm1, %ymm1
 ; AVX512VL-NEXT:    vscalefps %ymm1, %ymm0, %ymm0
 ; AVX512VL-NEXT:    retq
+;
+; AVX512VLFP16-LABEL: test_ldexp_8xfloat:
+; AVX512VLFP16:       # %bb.0:
+; AVX512VLFP16-NEXT:    vcvtdq2ps %ymm1, %ymm1
+; AVX512VLFP16-NEXT:    vscalefps %ymm1, %ymm0, %ymm0
+; AVX512VLFP16-NEXT:    retq
   %r = call <8 x float> @llvm.ldexp.v8f32.v8i32(<8 x float> %x, <8 x i32> %exp)
   ret <8 x float> %r
 }
@@ -715,30 +698,23 @@ declare <8 x float> @llvm.ldexp.v8f32.v8i32(<8 x float>, <8 x i32>)
 define <4 x double> @test_ldexp_4xdouble(<4 x double> %x, <4 x i32> %exp) nounwind {
 ; AVX512-LABEL: test_ldexp_4xdouble:
 ; AVX512:       # %bb.0:
-; AVX512-NEXT:    vextractf128 $1, %ymm0, %xmm2
-; AVX512-NEXT:    vshufps {{.*#+}} xmm3 = xmm1[2,3,2,3]
-; AVX512-NEXT:    vcvtdq2pd %xmm3, %xmm3
-; AVX512-NEXT:    vscalefsd %xmm3, %xmm2, %xmm3
-; AVX512-NEXT:    vcvtdq2pd %xmm1, %xmm4
-; AVX512-NEXT:    vscalefsd %xmm4, %xmm0, %xmm4
-; AVX512-NEXT:    vinsertf128 $1, %xmm3, %ymm4, %ymm3
-; AVX512-NEXT:    vshufps {{.*#+}} xmm4 = xmm1[3,3,3,3]
-; AVX512-NEXT:    vcvtdq2pd %xmm4, %xmm4
-; AVX512-NEXT:    vshufpd {{.*#+}} xmm2 = xmm2[1,0]
-; AVX512-NEXT:    vscalefsd %xmm4, %xmm2, %xmm2
-; AVX512-NEXT:    vshufps {{.*#+}} xmm1 = xmm1[1,1,1,1]
-; AVX512-NEXT:    vcvtdq2pd %xmm1, %xmm1
-; AVX512-NEXT:    vshufpd {{.*#+}} xmm0 = xmm0[1,0]
-; AVX512-NEXT:    vscalefsd %xmm1, %xmm0, %xmm0
-; AVX512-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
-; AVX512-NEXT:    vunpcklpd {{.*#+}} ymm0 = ymm3[0],ymm0[0],ymm3[2],ymm0[2]
+; AVX512-NEXT:    # kill: def $ymm0 killed $ymm0 def $zmm0
+; AVX512-NEXT:    vcvtdq2pd %xmm1, %ymm1
+; AVX512-NEXT:    vscalefpd %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    # kill: def $ymm0 killed $ymm0 killed $zmm0
 ; AVX512-NEXT:    retq
 ;
 ; AVX512VL-LABEL: test_ldexp_4xdouble:
 ; AVX512VL:       # %bb.0:
 ; AVX512VL-NEXT:    vcvtdq2pd %xmm1, %ymm1
 ; AVX512VL-NEXT:    vscalefpd %ymm1, %ymm0, %ymm0
 ; AVX512VL-NEXT:    retq
+;
+; AVX512VLFP16-LABEL: test_ldexp_4xdouble:
+; AVX512VLFP16:       # %bb.0:
+; AVX512VLFP16-NEXT:    vcvtdq2pd %xmm1, %ymm1
+; AVX512VLFP16-NEXT:    vscalefpd %ymm1, %ymm0, %ymm0
+; AVX512VLFP16-NEXT:    retq
   %r = call <4 x double> @llvm.ldexp.v4f64.v4i32(<4 x double> %x, <4 x i32> %exp)
   ret <4 x double> %r
 }
@@ -1495,3 +1471,5 @@ define <8 x double> @test_ldexp_8xdouble(<8 x double> %x, <8 x i32> %exp) nounwi
 }
 declare <8 x double> @llvm.ldexp.v8f64.v8i32(<8 x double>, <8 x i32>)
 
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; AVX512VLF: {{.*}}
