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mikhailramalhomikhailramalho
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[RISCV][VLOPT] Added support for the zvbc and the remaining zvbb instructions (#153234)
Follow-up PR to #153071, adding the remaining zvbb instructions (VBREV8_V and VREV8_V), plus the zvbc instruction (VCLMUL_VV, VCLMUL_VX, VCLMULH_VV, VCLMULH_VX).
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-12
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-12
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‎llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp‎

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -497,6 +497,10 @@ getOperandLog2EEW(const MachineOperand &MO, const MachineRegisterInfo *MRI) {
497497
case RISCV::VANDN_VX:
498498
// Vector Reverse Bits in Elements
499499
case RISCV::VBREV_V:
500+
// Vector Reverse Bits in Bytes
501+
case RISCV::VBREV8_V:
502+
// Vector Reverse Bytes
503+
case RISCV::VREV8_V:
500504
// Vector Count Leading Zeros
501505
case RISCV::VCLZ_V:
502506
// Vector Count Trailing Zeros
@@ -510,6 +514,13 @@ getOperandLog2EEW(const MachineOperand &MO, const MachineRegisterInfo *MRI) {
510514
case RISCV::VROR_VI:
511515
case RISCV::VROR_VV:
512516
case RISCV::VROR_VX:
517+
// Vector Carry-less Multiplication Instructions (Zvbc)
518+
// Vector Carry-less Multiply
519+
case RISCV::VCLMUL_VV:
520+
case RISCV::VCLMUL_VX:
521+
// Vector Carry-less Multiply Return High Half
522+
case RISCV::VCLMULH_VV:
523+
case RISCV::VCLMULH_VX:
513524
return MILog2SEW;
514525

515526
// Vector Widening Shift Left Logical (Zvbb)
@@ -1046,6 +1057,10 @@ static bool isSupportedInstr(const MachineInstr &MI) {
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case RISCV::VANDN_VX:
10471058
// Vector Reverse Bits in Elements
10481059
case RISCV::VBREV_V:
1060+
// Vector Reverse Bits in Bytes
1061+
case RISCV::VBREV8_V:
1062+
// Vector Reverse Bytes
1063+
case RISCV::VREV8_V:
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// Vector Count Leading Zeros
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case RISCV::VCLZ_V:
10511066
// Vector Count Trailing Zeros
@@ -1063,6 +1078,13 @@ static bool isSupportedInstr(const MachineInstr &MI) {
10631078
case RISCV::VWSLL_VI:
10641079
case RISCV::VWSLL_VX:
10651080
case RISCV::VWSLL_VV:
1081+
// Vector Carry-less Multiplication Instructions (Zvbc)
1082+
// Vector Carry-less Multiply
1083+
case RISCV::VCLMUL_VV:
1084+
case RISCV::VCLMUL_VX:
1085+
// Vector Carry-less Multiply Return High Half
1086+
case RISCV::VCLMULH_VV:
1087+
case RISCV::VCLMULH_VX:
10661088
// Vector Mask Instructions
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// Vector Mask-Register Logical Instructions
10681090
// vmsbf.m set-before-first mask bit

‎llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll‎

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -3438,9 +3438,8 @@ define <vscale x 4 x i32> @vbrev_v(<vscale x 4 x i32> %a, iXLen %vl) {
34383438
define <vscale x 4 x i32> @vbrev8_v(<vscale x 4 x i32> %a, iXLen %vl) {
34393439
; CHECK-LABEL: vbrev8_v:
34403440
; CHECK: # %bb.0:
3441-
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
3442-
; CHECK-NEXT: vbrev8.v v10, v8
34433441
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
3442+
; CHECK-NEXT: vbrev8.v v10, v8
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; CHECK-NEXT: vadd.vv v8, v10, v8
34453444
; CHECK-NEXT: ret
34463445
%1 = call <vscale x 4 x i32> @llvm.riscv.vbrev8.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> %a, iXLen -1)
@@ -3451,9 +3450,8 @@ define <vscale x 4 x i32> @vbrev8_v(<vscale x 4 x i32> %a, iXLen %vl) {
34513450
define <vscale x 4 x i32> @vrev8_v(<vscale x 4 x i32> %a, iXLen %vl) {
34523451
; CHECK-LABEL: vrev8_v:
34533452
; CHECK: # %bb.0:
3454-
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
3455-
; CHECK-NEXT: vrev8.v v10, v8
34563453
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
3454+
; CHECK-NEXT: vrev8.v v10, v8
34573455
; CHECK-NEXT: vadd.vv v8, v10, v8
34583456
; CHECK-NEXT: ret
34593457
%1 = call <vscale x 4 x i32> @llvm.riscv.vrev8.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> %a, iXLen -1)
@@ -3560,9 +3558,8 @@ define <vscale x 4 x i32> @vrol_vx(<vscale x 4 x i32> %a, iXLen %b, iXLen %vl) {
35603558
define <vscale x 2 x i64> @vclmul_vv(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, iXLen %vl) {
35613559
; CHECK-LABEL: vclmul_vv:
35623560
; CHECK: # %bb.0:
3563-
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma
3564-
; CHECK-NEXT: vclmul.vv v10, v8, v10
35653561
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
3562+
; CHECK-NEXT: vclmul.vv v10, v8, v10
35663563
; CHECK-NEXT: vadd.vv v8, v10, v8
35673564
; CHECK-NEXT: ret
35683565
%1 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b, iXLen -1)
@@ -3573,9 +3570,8 @@ define <vscale x 2 x i64> @vclmul_vv(<vscale x 2 x i64> %a, <vscale x 2 x i64> %
35733570
define <vscale x 2 x i64> @vclmul_vx(<vscale x 2 x i64> %a, i32 %b, iXLen %vl) {
35743571
; CHECK-LABEL: vclmul_vx:
35753572
; CHECK: # %bb.0:
3576-
; CHECK-NEXT: vsetvli a2, zero, e64, m2, ta, ma
3577-
; CHECK-NEXT: vclmul.vx v10, v8, a0
35783573
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
3574+
; CHECK-NEXT: vclmul.vx v10, v8, a0
35793575
; CHECK-NEXT: vadd.vv v8, v10, v8
35803576
; CHECK-NEXT: ret
35813577
%1 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i32(<vscale x 2 x i64> undef, <vscale x 2 x i64> %a, i32 %b, iXLen -1)
@@ -3586,9 +3582,8 @@ define <vscale x 2 x i64> @vclmul_vx(<vscale x 2 x i64> %a, i32 %b, iXLen %vl) {
35863582
define <vscale x 2 x i64> @vclmulh_vv(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, iXLen %vl) {
35873583
; CHECK-LABEL: vclmulh_vv:
35883584
; CHECK: # %bb.0:
3589-
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma
3590-
; CHECK-NEXT: vclmulh.vv v10, v8, v10
35913585
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
3586+
; CHECK-NEXT: vclmulh.vv v10, v8, v10
35923587
; CHECK-NEXT: vadd.vv v8, v10, v8
35933588
; CHECK-NEXT: ret
35943589
%1 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b, iXLen -1)
@@ -3599,9 +3594,8 @@ define <vscale x 2 x i64> @vclmulh_vv(<vscale x 2 x i64> %a, <vscale x 2 x i64>
35993594
define <vscale x 2 x i64> @vclmulh_vx(<vscale x 2 x i64> %a, i32 %b, iXLen %vl) {
36003595
; CHECK-LABEL: vclmulh_vx:
36013596
; CHECK: # %bb.0:
3602-
; CHECK-NEXT: vsetvli a2, zero, e64, m2, ta, ma
3603-
; CHECK-NEXT: vclmulh.vx v10, v8, a0
36043597
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
3598+
; CHECK-NEXT: vclmulh.vx v10, v8, a0
36053599
; CHECK-NEXT: vadd.vv v8, v10, v8
36063600
; CHECK-NEXT: ret
36073601
%1 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i32(<vscale x 2 x i64> undef, <vscale x 2 x i64> %a, i32 %b, iXLen -1)

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