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fixup! Fix RVE register lists. Simplify F32_V and F64_V lists.
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llvm/lib/Target/RISCV/RISCVCallingConv.td

Lines changed: 8 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -62,14 +62,12 @@ def CSR_XLEN_V_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,
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// Same as CSR_Interrupt, but including all 32-bit FP registers and all vector
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// registers.
65-
def CSR_XLEN_F32_V_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,
66-
(sequence "F%u_F", 0, 31),
65+
def CSR_XLEN_F32_V_Interrupt: CalleeSavedRegs<(add CSR_XLEN_F32_Interrupt,
6766
(sequence "V%u", 0, 31))>;
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// Same as CSR_Interrupt, but including all 64-bit FP registers and all vector
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// registers.
71-
def CSR_XLEN_F64_V_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,
72-
(sequence "F%u_D", 0, 31),
70+
def CSR_XLEN_F64_V_Interrupt: CalleeSavedRegs<(add CSR_XLEN_F64_Interrupt,
7371
(sequence "V%u", 0, 31))>;
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// Same as CSR_Interrupt, but excluding X16-X31.
@@ -85,15 +83,13 @@ def CSR_XLEN_F64_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_F64_Interrupt,
8583
(sequence "X%u", 16, 31))>;
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// Same as CSR_XLEN_V_Interrupt, but excluding X16-X31.
88-
def CSR_XLEN_V_Interrupt_RVE: CalleeSavedRegs<(add CSR_Interrupt,
89-
(sequence "V%u", 0, 31))>;
86+
def CSR_XLEN_V_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_V_Interrupt,
87+
(sequence "X%u", 16, 31))>;
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// Same as CSR_XLEN_F32_V_Interrupt, but excluding X16-X31.
92-
def CSR_XLEN_F32_V_Interrupt_RVE: CalleeSavedRegs<(add CSR_Interrupt,
93-
(sequence "F%u_F", 0, 31),
94-
(sequence "V%u", 0, 31))>;
90+
def CSR_XLEN_F32_V_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_F32_V_Interrupt,
91+
(sequence "X%u", 16, 31))>;
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// Same as CSR_XLEN_F64_V_Interrupt, but excluding X16-X31.
97-
def CSR_XLEN_F64_V_Interrupt_RVE: CalleeSavedRegs<(add CSR_Interrupt,
98-
(sequence "F%u_D", 0, 31),
99-
(sequence "V%u", 0, 31))>;
94+
def CSR_XLEN_F64_V_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_F64_V_Interrupt,
95+
(sequence "X%u", 16, 31))>;

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