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[AMDGPU][Attributor] Infer inreg attribute in AMDGPUAttributor
This patch introduces `AAAMDGPUUniformArgument` that can infer `inreg` function argument attribute. The idea is, for a function argument, if the corresponding call site arguments are always uniform, we can mark it as `inreg` thus pass it via SGPR. In addition, this AA is also able to propagate the inreg attribute if feasible.
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‎llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp‎

Lines changed: 115 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@
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#include "AMDGPU.h"
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#include "GCNSubtarget.h"
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#include "Utils/AMDGPUBaseInfo.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/IntrinsicsAMDGPU.h"
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#include "llvm/IR/IntrinsicsR600.h"
@@ -1297,6 +1298,114 @@ struct AAAMDGPUNoAGPR
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12981299
const char AAAMDGPUNoAGPR::ID = 0;
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1301+
struct AAAMDGPUUniform : public StateWrapper<BooleanState, AbstractAttribute> {
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using Base = StateWrapper<BooleanState, AbstractAttribute>;
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AAAMDGPUUniform(const IRPosition &IRP, Attributor &A) : Base(IRP) {}
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/// Create an abstract attribute view for the position \p IRP.
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static AAAMDGPUUniform &createForPosition(const IRPosition &IRP,
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Attributor &A);
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/// See AbstractAttribute::getName()
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StringRef getName() const override { return "AAAMDGPUUniform"; }
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const std::string getAsStr(Attributor *A) const override {
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return getAssumed() ? "uniform" : "divergent";
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}
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void trackStatistics() const override {}
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/// See AbstractAttribute::getIdAddr()
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const char *getIdAddr() const override { return &ID; }
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/// This function should return true if the type of the \p AA is
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/// AAAMDGPUUniform
1323+
static bool classof(const AbstractAttribute *AA) {
1324+
return (AA->getIdAddr() == &ID);
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}
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/// Unique ID (due to the unique address)
1328+
static const char ID;
1329+
};
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1331+
const char AAAMDGPUUniform::ID = 0;
1332+
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/// This AA is to infer the inreg attribute for a function argument.
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struct AAAMDGPUUniformArgument : public AAAMDGPUUniform {
1335+
AAAMDGPUUniformArgument(const IRPosition &IRP, Attributor &A)
1336+
: AAAMDGPUUniform(IRP, A) {}
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void initialize(Attributor &A) override {
1339+
Argument *Arg = getAssociatedArgument();
1340+
CallingConv::ID CC = Arg->getParent()->getCallingConv();
1341+
if (Arg->hasAttribute(Attribute::InReg)) {
1342+
indicateOptimisticFixpoint();
1343+
return;
1344+
}
1345+
1346+
if (AMDGPU::isEntryFunctionCC(CC)) {
1347+
// We only use isArgPassedInSGPR on kernel entry function argument, so
1348+
// even if we will use SPGR for non-uniform i1 argument passing, it will
1349+
// not affect this.
1350+
if (AMDGPU::isArgPassedInSGPR(Arg))
1351+
indicateOptimisticFixpoint();
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else
1353+
indicatePessimisticFixpoint();
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}
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}
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ChangeStatus updateImpl(Attributor &A) override {
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unsigned ArgNo = getAssociatedArgument()->getArgNo();
1359+
TargetMachine &TM =
1360+
static_cast<AMDGPUInformationCache &>(A.getInfoCache()).TM;
1361+
1362+
auto isUniform = [&](AbstractCallSite ACS) -> bool {
1363+
CallBase *CB = ACS.getInstruction();
1364+
Value *V = CB->getArgOperand(ArgNo);
1365+
if (auto *Arg = dyn_cast<Argument>(V)) {
1366+
auto *AA = A.getOrCreateAAFor<AAAMDGPUUniform>(
1367+
IRPosition::argument(*Arg), this, DepClassTy::REQUIRED);
1368+
return AA && AA->isValidState();
1369+
}
1370+
TargetTransformInfo TTI = TM.getTargetTransformInfo(*CB->getFunction());
1371+
return TTI.isAlwaysUniform(V);
1372+
};
1373+
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bool UsedAssumedInformation = true;
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if (!A.checkForAllCallSites(isUniform, *this, /*RequireAllCallSites=*/true,
1376+
UsedAssumedInformation))
1377+
return indicatePessimisticFixpoint();
1378+
1379+
if (!UsedAssumedInformation)
1380+
return indicateOptimisticFixpoint();
1381+
1382+
return ChangeStatus::UNCHANGED;
1383+
}
1384+
1385+
ChangeStatus manifest(Attributor &A) override {
1386+
Argument *Arg = getAssociatedArgument();
1387+
// If the argument already has inreg attribute, we will not do anything
1388+
// about it.
1389+
if (Arg->hasAttribute(Attribute::InReg))
1390+
return ChangeStatus::UNCHANGED;
1391+
if (AMDGPU::isEntryFunctionCC(Arg->getParent()->getCallingConv()))
1392+
return ChangeStatus::UNCHANGED;
1393+
LLVMContext &Ctx = Arg->getContext();
1394+
return A.manifestAttrs(getIRPosition(),
1395+
{Attribute::get(Ctx, Attribute::InReg)});
1396+
}
1397+
};
1398+
1399+
AAAMDGPUUniform &AAAMDGPUUniform::createForPosition(const IRPosition &IRP,
1400+
Attributor &A) {
1401+
switch (IRP.getPositionKind()) {
1402+
case IRPosition::IRP_ARGUMENT:
1403+
return *new (A.Allocator) AAAMDGPUUniformArgument(IRP, A);
1404+
default:
1405+
llvm_unreachable("not a valid position for AAAMDGPUUniform");
1406+
}
1407+
}
1408+
13001409
/// Performs the final check and updates the 'amdgpu-waves-per-eu' attribute
13011410
/// based on the finalized 'amdgpu-flat-work-group-size' attribute.
13021411
/// Both attributes start with narrow ranges that expand during iteration.
@@ -1383,7 +1492,7 @@ static bool runImpl(Module &M, AnalysisGetter &AG, TargetMachine &TM,
13831492
&AAAMDMaxNumWorkgroups::ID, &AAAMDWavesPerEU::ID, &AAAMDGPUNoAGPR::ID,
13841493
&AACallEdges::ID, &AAPointerInfo::ID, &AAPotentialConstantValues::ID,
13851494
&AAUnderlyingObjects::ID, &AANoAliasAddrSpace::ID, &AAAddressSpace::ID,
1386-
&AAIndirectCallInfo::ID, &AAInstanceInfo::ID});
1495+
&AAIndirectCallInfo::ID, &AAInstanceInfo::ID, &AAAMDGPUUniform::ID});
13871496

13881497
AttributorConfig AC(CGUpdater);
13891498
AC.IsClosedWorldModule = Options.IsClosedWorld;
@@ -1436,6 +1545,11 @@ static bool runImpl(Module &M, AnalysisGetter &AG, TargetMachine &TM,
14361545
A.getOrCreateAAFor<AAAddressSpace>(IRPosition::value(*Ptr));
14371546
A.getOrCreateAAFor<AANoAliasAddrSpace>(IRPosition::value(*Ptr));
14381547
}
1548+
1549+
if (!AMDGPU::isEntryFunctionCC(F->getCallingConv())) {
1550+
for (auto &Arg : F->args())
1551+
A.getOrCreateAAFor<AAAMDGPUUniform>(IRPosition::argument(Arg));
1552+
}
14391553
}
14401554
}
14411555

‎llvm/test/CodeGen/AMDGPU/aa-inreg-inference.ll‎

Lines changed: 74 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,74 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
2+
; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-attributor %s -o - | FileCheck %s
3+
4+
@g1 = protected addrspace(1) externally_initialized global i32 0, align 4
5+
@g2 = protected addrspace(1) externally_initialized global i32 0, align 4
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@g3 = protected addrspace(1) externally_initialized global i32 0, align 4
7+
@g4 = protected addrspace(1) externally_initialized global i32 0, align 4
8+
9+
define internal void @callee_with_always_uniform_argument(ptr addrspace(1) %x, i32 %y) {
10+
; CHECK-LABEL: define internal void @callee_with_always_uniform_argument(
11+
; CHECK-SAME: ptr addrspace(1) inreg [[X:%.*]], i32 inreg [[Y:%.*]]) #[[ATTR0:[0-9]+]] {
12+
; CHECK-NEXT: [[ENTRY:.*:]]
13+
; CHECK-NEXT: [[X_VAL:%.*]] = load i32, ptr addrspace(1) [[X]], align 4
14+
; CHECK-NEXT: store i32 [[X_VAL]], ptr addrspace(1) @g3, align 4
15+
; CHECK-NEXT: store i32 [[Y]], ptr addrspace(1) @g4, align 4
16+
; CHECK-NEXT: ret void
17+
;
18+
entry:
19+
%x.val = load i32, ptr addrspace(1) %x, align 4
20+
store i32 %x.val, ptr addrspace(1) @g3, align 4
21+
store i32 %y, ptr addrspace(1) @g4, align 4
22+
ret void
23+
}
24+
25+
define amdgpu_kernel void @kernel_with_readfirstlane(ptr addrspace(1) %p, i32 %x) {
26+
; CHECK-LABEL: define amdgpu_kernel void @kernel_with_readfirstlane(
27+
; CHECK-SAME: ptr addrspace(1) [[P:%.*]], i32 [[X:%.*]]) #[[ATTR0]] {
28+
; CHECK-NEXT: [[ENTRY:.*:]]
29+
; CHECK-NEXT: [[P0:%.*]] = call ptr addrspace(1) @llvm.amdgcn.readfirstlane.p1(ptr addrspace(1) [[P]])
30+
; CHECK-NEXT: call void @callee_with_always_uniform_argument(ptr addrspace(1) [[P0]], i32 [[X]])
31+
; CHECK-NEXT: ret void
32+
;
33+
entry:
34+
%p0 = call ptr addrspace(1) @llvm.amdgcn.readfirstlane.p1(ptr addrspace(1) %p)
35+
call void @callee_with_always_uniform_argument(ptr addrspace(1) %p0, i32 %x)
36+
ret void
37+
}
38+
39+
define internal void @callee_without_always_uniform_argument(ptr addrspace(1) %x, i32 %y) {
40+
; CHECK-LABEL: define internal void @callee_without_always_uniform_argument(
41+
; CHECK-SAME: ptr addrspace(1) [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR0]] {
42+
; CHECK-NEXT: [[ENTRY:.*:]]
43+
; CHECK-NEXT: [[X_VAL:%.*]] = load i32, ptr addrspace(1) [[X]], align 4
44+
; CHECK-NEXT: store i32 [[X_VAL]], ptr addrspace(1) @g3, align 4
45+
; CHECK-NEXT: store i32 [[Y]], ptr addrspace(1) @g4, align 4
46+
; CHECK-NEXT: ret void
47+
;
48+
entry:
49+
%x.val = load i32, ptr addrspace(1) %x, align 4
50+
store i32 %x.val, ptr addrspace(1) @g3, align 4
51+
store i32 %y, ptr addrspace(1) @g4, align 4
52+
ret void
53+
}
54+
55+
define amdgpu_kernel void @kernel_with_divergent_callsite_argument(ptr addrspace(1) %p, i32 %x) {
56+
; CHECK-LABEL: define amdgpu_kernel void @kernel_with_divergent_callsite_argument(
57+
; CHECK-SAME: ptr addrspace(1) [[P:%.*]], i32 [[X:%.*]]) #[[ATTR0]] {
58+
; CHECK-NEXT: [[ENTRY:.*:]]
59+
; CHECK-NEXT: [[ID_X:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
60+
; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr addrspace(1) [[P]], i32 [[ID_X]]
61+
; CHECK-NEXT: [[D:%.*]] = load i32, ptr addrspace(1) [[GEP]], align 4
62+
; CHECK-NEXT: call void @callee_without_always_uniform_argument(ptr addrspace(1) [[GEP]], i32 [[D]])
63+
; CHECK-NEXT: ret void
64+
;
65+
entry:
66+
%id.x = call i32 @llvm.amdgcn.workitem.id.x()
67+
%gep = getelementptr i32, ptr addrspace(1) %p, i32 %id.x
68+
%d = load i32, ptr addrspace(1) %gep
69+
call void @callee_without_always_uniform_argument(ptr addrspace(1) %gep, i32 %d)
70+
ret void
71+
}
72+
73+
declare ptr addrspace(1) @llvm.amdgcn.readfirstlane.p1(ptr addrspace(1))
74+
declare noundef i32 @llvm.amdgcn.workitem.id.x()

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