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[Xtensa] Add esp32/esp8266 cpus implementation. (#152409)
Add Xtensa esp32 and esp8266 cpus. Implement target parser to recognise Xtensa hardware features.
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‎llvm/include/llvm/TargetParser/XtensaTargetParser.def‎

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//===- XtensaTargetParser.def - Xtensa target parsing defines ---*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides defines to build up the Xtensa target parser's logic.
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//
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//===----------------------------------------------------------------------===//
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#ifndef XTENSA_FEATURE
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#define XTENSA_FEATURE(ID, STR)
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#endif
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XTENSA_FEATURE(XF_DENSITY, "density")
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XTENSA_FEATURE(XF_FP, "fp")
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XTENSA_FEATURE(XF_WINDOWED, "windowed")
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XTENSA_FEATURE(XF_BOOLEAN, "bool")
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XTENSA_FEATURE(XF_LOOP, "loop")
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XTENSA_FEATURE(XF_SEXT, "sext")
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XTENSA_FEATURE(XF_NSA, "nsa")
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XTENSA_FEATURE(XF_CLAMPS, "clamps")
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XTENSA_FEATURE(XF_MINMAX, "minmax")
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XTENSA_FEATURE(XF_MAC16, "mac16")
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XTENSA_FEATURE(XF_MUL32, "mul32")
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XTENSA_FEATURE(XF_MUL32HIGH, "mul32high")
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XTENSA_FEATURE(XF_DIV32, "div32")
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XTENSA_FEATURE(XF_MUL16, "mul16")
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XTENSA_FEATURE(XF_DFPACCEL, "dfpaccel")
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XTENSA_FEATURE(XF_S32C1I, "s32c1i")
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XTENSA_FEATURE(XF_THREADPTR, "threadptr")
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XTENSA_FEATURE(XF_EXTENDEDL32R, "extendedl32r")
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XTENSA_FEATURE(XF_DATACACHE, "dcache")
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XTENSA_FEATURE(XF_DEBUG, "debug")
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XTENSA_FEATURE(XF_EXCEPTION, "exception")
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XTENSA_FEATURE(XF_HIGHPRIINTERRUPTS, "highpriinterrupts")
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XTENSA_FEATURE(XF_HIGHPRIINTERRUPTSLEVEL3, "highpriinterruptslevel3")
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XTENSA_FEATURE(XF_HIGHPRIINTERRUPTSLEVEL4, "highpriinterruptslevel4")
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XTENSA_FEATURE(XF_HIGHPRIINTERRUPTSLEVEL5, "highpriinterruptslevel5")
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XTENSA_FEATURE(XF_HIGHPRIINTERRUPTSLEVEL6, "highpriinterruptslevel6")
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XTENSA_FEATURE(XF_HIGHPRIINTERRUPTSLEVEL7, "highpriinterruptslevel7")
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XTENSA_FEATURE(XF_COPROCESSOR, "coprocessor")
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XTENSA_FEATURE(XF_INTERRUPT, "interrupt")
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XTENSA_FEATURE(XF_RVECTOR, "rvector")
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XTENSA_FEATURE(XF_TIMERS1, "timers1")
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XTENSA_FEATURE(XF_TIMERS2, "timers2")
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XTENSA_FEATURE(XF_TIMERS3, "timers3")
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XTENSA_FEATURE(XF_PRID, "prid")
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XTENSA_FEATURE(XF_REGPROTECT, "regprotect")
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XTENSA_FEATURE(XF_MISCSR, "miscsr")
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#undef XTENSA_FEATURE
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#ifndef XTENSA_CPU
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#define XTENSA_CPU(ENUM, NAME, FEATURES)
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#endif
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XTENSA_CPU(INVALID, {"invalid"}, XF_INVALID)
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XTENSA_CPU(GENERIC, {"generic"}, XF_NONE)
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XTENSA_CPU(ESP8266, {"esp8266"},
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(XF_DENSITY | XF_NSA | XF_MUL16 | XF_MUL32 | XF_EXTENDEDL32R | XF_DEBUG | XF_EXCEPTION |
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XF_HIGHPRIINTERRUPTS | XF_HIGHPRIINTERRUPTSLEVEL3 | XF_INTERRUPT | XF_RVECTOR | XF_TIMERS1 |
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XF_REGPROTECT | XF_PRID))
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XTENSA_CPU(ESP32, {"esp32"},
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(XF_DENSITY | XF_FP | XF_LOOP | XF_MAC16 | XF_WINDOWED | XF_BOOLEAN | XF_SEXT | XF_NSA |
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XF_CLAMPS | XF_MINMAX | XF_MUL32 | XF_MUL32HIGH | XF_MUL16 | XF_DFPACCEL | XF_S32C1I |
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XF_THREADPTR | XF_DIV32 | XF_DATACACHE | XF_DEBUG | XF_EXCEPTION | XF_HIGHPRIINTERRUPTS |
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XF_HIGHPRIINTERRUPTSLEVEL7 | XF_COPROCESSOR | XF_INTERRUPT | XF_RVECTOR | XF_TIMERS3 | XF_PRID |
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XF_REGPROTECT | XF_MISCSR))
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#undef XTENSA_CPU
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#ifndef XTENSA_CPU_ALIAS
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#define XTENSA_CPU_ALIAS(NAME, ALTNMAME)
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#endif
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#undef XTENSA_CPU_ALIAS

‎llvm/include/llvm/TargetParser/XtensaTargetParser.h‎

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//===----------------------------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file implements a target parser to recognise Xtensa hardware features.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGETPARSER_XTENSATARGETPARSER_H
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#define LLVM_TARGETPARSER_XTENSATARGETPARSER_H
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#include "llvm/TargetParser/Triple.h"
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#include <vector>
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namespace llvm {
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class StringRef;
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namespace Xtensa {
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enum CPUKind : unsigned {
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#define XTENSA_CPU(ENUM, NAME, FEATURES) CK_##ENUM,
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#include "XtensaTargetParser.def"
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};
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enum XtensaFeatureKind : uint64_t {
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XF_INVALID = 0,
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XF_NONE = 1,
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XF_FP = 1 << 1,
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XF_WINDOWED = 1 << 2,
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XF_BOOLEAN = 1 << 3,
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XF_DENSITY = 1 << 4,
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XF_LOOP = 1 << 5,
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XF_SEXT = 1 << 6,
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XF_NSA = 1 << 7,
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XF_CLAMPS = 1 << 8,
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XF_MINMAX = 1 << 9,
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XF_MAC16 = 1 << 10,
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XF_MUL32 = 1 << 11,
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XF_MUL32HIGH = 1 << 12,
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XF_DIV32 = 1 << 13,
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XF_MUL16 = 1 << 14,
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XF_DFPACCEL = 1 << 15,
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XF_S32C1I = 1 << 16,
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XF_THREADPTR = 1 << 17,
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XF_EXTENDEDL32R = 1 << 18,
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XF_DATACACHE = 1 << 19,
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XF_DEBUG = 1 << 20,
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XF_EXCEPTION = 1 << 21,
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XF_HIGHPRIINTERRUPTS = 1 << 22,
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XF_HIGHPRIINTERRUPTSLEVEL3 = 1 << 23,
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XF_HIGHPRIINTERRUPTSLEVEL4 = 1 << 24,
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XF_HIGHPRIINTERRUPTSLEVEL5 = 1 << 25,
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XF_HIGHPRIINTERRUPTSLEVEL6 = 1 << 26,
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XF_HIGHPRIINTERRUPTSLEVEL7 = 1 << 27,
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XF_COPROCESSOR = 1 << 28,
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XF_INTERRUPT = 1 << 29,
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XF_RVECTOR = 1 << 30,
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XF_TIMERS1 = 1ULL << 31,
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XF_TIMERS2 = 1ULL << 32,
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XF_TIMERS3 = 1ULL << 33,
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XF_PRID = 1ULL << 34,
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XF_REGPROTECT = 1ULL << 35,
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XF_MISCSR = 1ULL << 36
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};
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CPUKind parseCPUKind(StringRef CPU);
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StringRef getBaseName(StringRef CPU);
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void getCPUFeatures(StringRef CPU, SmallVectorImpl<StringRef> &Features);
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void fillValidCPUList(SmallVectorImpl<StringRef> &Values);
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} // namespace Xtensa
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} // namespace llvm
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#endif // LLVM_SUPPORT_XTENSATARGETPARSER_H

‎llvm/include/module.modulemap‎

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textual header "llvm/TargetParser/X86TargetParser.def"
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textual header "llvm/TargetParser/LoongArchTargetParser.def"
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textual header "llvm/TargetParser/PPCTargetParser.def"
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textual header "llvm/TargetParser/XtensaTargetParser.def"
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}
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// This part of the module is usable from both C and C++ code.

‎llvm/lib/Target/Xtensa/Xtensa.td‎

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//===----------------------------------------------------------------------===//
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// Xtensa supported processors.
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//===----------------------------------------------------------------------===//
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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def : Proc<"generic", []>;
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include "XtensaProcessors.td"
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//===----------------------------------------------------------------------===//
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// Register File Description

‎llvm/lib/Target/Xtensa/XtensaProcessors.td‎

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//===- XtensaProcessors.td - Xtensa Processors -------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Xtensa supported processors.
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//===----------------------------------------------------------------------===//
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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def : Proc<"generic", []>;
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def : Proc<"esp32", [FeatureDensity, FeatureSingleFloat, FeatureLoop, FeatureMAC16, FeatureWindowed, FeatureBoolean, FeatureSEXT,
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FeatureNSA, FeatureMul16, FeatureMul32, FeatureMul32High, FeatureDFPAccel, FeatureS32C1I, FeatureTHREADPTR, FeatureDiv32,
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FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureHighPriInterruptsLevel7, FeatureCoprocessor,
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FeatureInterrupt, FeatureDataCache, FeatureRelocatableVector, FeatureTimers3, FeaturePRID, FeatureRegionProtection, FeatureMiscSR,
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FeatureMINMAX, FeatureCLAMPS]>;
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def : Proc<"esp8266", [FeatureDensity, FeatureNSA, FeatureMul16, FeatureMul32, FeatureExtendedL32R, FeatureDebug, FeatureException,
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FeatureHighPriInterrupts, FeatureHighPriInterruptsLevel3, FeatureInterrupt, FeatureRelocatableVector, FeatureTimers1,
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FeatureRegionProtection, FeaturePRID]>;

‎llvm/lib/TargetParser/CMakeLists.txt‎

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TargetParser.cpp
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Triple.cpp
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X86TargetParser.cpp
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XtensaTargetParser.cpp
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ADDITIONAL_HEADER_DIRS
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Unix

‎llvm/lib/TargetParser/XtensaTargetParser.cpp‎

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//==-- XtensaTargetParser - Parser for Xtensa features ------------*- C++ -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a target parser to recognise Xtensa hardware features
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/TargetParser/XtensaTargetParser.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/StringSwitch.h"
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namespace llvm {
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namespace Xtensa {
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struct CPUInfo {
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StringLiteral Name;
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CPUKind Kind;
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uint64_t Features;
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};
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struct FeatureName {
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uint64_t ID;
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const char *NameCStr;
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size_t NameLength;
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StringRef getName() const { return StringRef(NameCStr, NameLength); }
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};
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const FeatureName XtensaFeatureNames[] = {
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#define XTENSA_FEATURE(ID, NAME) {ID, "+" NAME, sizeof(NAME)},
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#include "llvm/TargetParser/XtensaTargetParser.def"
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};
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constexpr CPUInfo XtensaCPUInfo[] = {
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#define XTENSA_CPU(ENUM, NAME, FEATURES) {NAME, CK_##ENUM, FEATURES},
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#include "llvm/TargetParser/XtensaTargetParser.def"
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};
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StringRef getBaseName(StringRef CPU) {
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return llvm::StringSwitch<StringRef>(CPU)
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#define XTENSA_CPU_ALIAS(NAME, ANAME) .Case(ANAME, NAME)
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#include "llvm/TargetParser/XtensaTargetParser.def"
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.Default(CPU);
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}
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StringRef getAliasName(StringRef CPU) {
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return llvm::StringSwitch<StringRef>(CPU)
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#define XTENSA_CPU_ALIAS(NAME, ANAME) .Case(NAME, ANAME)
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#include "llvm/TargetParser/XtensaTargetParser.def"
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.Default(CPU);
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}
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CPUKind parseCPUKind(StringRef CPU) {
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CPU = getBaseName(CPU);
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return llvm::StringSwitch<CPUKind>(CPU)
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#define XTENSA_CPU(ENUM, NAME, FEATURES) .Case(NAME, CK_##ENUM)
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#include "llvm/TargetParser/XtensaTargetParser.def"
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.Default(CK_INVALID);
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}
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// Get all features for the CPU
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void getCPUFeatures(StringRef CPU, std::vector<StringRef> &Features) {
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CPU = getBaseName(CPU);
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auto I = llvm::find_if(XtensaCPUInfo,
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[&](const CPUInfo &CI) { return CI.Name == CPU; });
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assert(I != std::end(XtensaCPUInfo) && "CPU not found!");
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uint64_t Bits = I->Features;
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for (const auto &F : XtensaFeatureNames) {
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if ((Bits & F.ID) == F.ID)
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Features.push_back(F.getName());
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}
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}
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// Find all valid CPUs
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void fillValidCPUList(std::vector<StringRef> &Values) {
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for (const auto &C : XtensaCPUInfo) {
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if (C.Kind != CK_INVALID) {
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Values.emplace_back(C.Name);
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StringRef Name = getAliasName(C.Name);
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if (Name != C.Name)
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Values.emplace_back(Name);
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}
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}
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}
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} // namespace Xtensa
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} // namespace llvm

‎llvm/test/CodeGen/Xtensa/cpus-invalid.ll‎

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; RUN: llc < %s --mtriple=xtensa --mcpu=invalid 2>&1 | FileCheck %s
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; CHECK: {{.*}} is not a recognized processor for this target
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define void @f() {
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ret void
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}
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‎llvm/test/CodeGen/Xtensa/cpus.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; This tests that llc accepts all valid Xtensa CPUs
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; RUN: llc < %s --mtriple=xtensa --mcpu=esp8266 2>&1 | FileCheck -check-prefix=XTENSA-ESP8266 %s
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; RUN: llc < %s --mtriple=xtensa --mcpu=esp32 2>&1 | FileCheck -check-prefix=XTENSA-ESP32 %s
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; RUN: llc < %s --mtriple=xtensa --mcpu=generic 2>&1 | FileCheck -check-prefix=XTENSA-GENERIC %s
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define i32 @f(i32 %z) {
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; XTENSA-ESP8266-LABEL: f:
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; XTENSA-ESP8266: .cfi_startproc
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; XTENSA-ESP8266-NEXT: # %bb.0:
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; XTENSA-ESP8266-NEXT: movi a2, 0
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; XTENSA-ESP8266-NEXT: ret
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;
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; XTENSA-ESP32-LABEL: f:
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; XTENSA-ESP32: .cfi_startproc
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; XTENSA-ESP32-NEXT: # %bb.0:
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; XTENSA-ESP32-NEXT: entry a1, 32
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; XTENSA-ESP32-NEXT: .cfi_def_cfa_offset 32
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; XTENSA-ESP32-NEXT: movi a2, 0
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; XTENSA-ESP32-NEXT: retw.n
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;
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; XTENSA-GENERIC-LABEL: f:
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; XTENSA-GENERIC: .cfi_startproc
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; XTENSA-GENERIC-NEXT: # %bb.0:
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; XTENSA-GENERIC-NEXT: movi a2, 0
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; XTENSA-GENERIC-NEXT: ret
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ret i32 0
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}

‎llvm/utils/gn/secondary/llvm/lib/TargetParser/BUILD.gn‎

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"TargetParser.cpp",
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"Triple.cpp",
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"X86TargetParser.cpp",
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"XtensaTargetParser.cpp",
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]
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}

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