Fix nomerge test comment

thurstond · thurstond · commit 48de3e069017 · 2024-11-26T18:17:25.000Z
diff --git a/llvm/test/CodeGen/X86/ubsan-trap-nomerge.ll b/llvm/test/CodeGen/X86/ubsan-trap-nomerge.ll
@@ -1,8 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -O3 -mtriple x86_64 -filetype asm -o - %s | FileCheck %s
 ;
-; This test shows that ubsantrap can, in the absence of nomerge, be merged by
-; the backend into a single ud1 instruction (thus making debugging difficult).
+; This tests that the nomerge attribute for ubsantrap works correctly i.e.,
+; they are lowered to separate ud1 instructions.
 ;
 ; The LLVM IR was generated from clang/test/CodeGen/ubsan-trap-merge.c with
 ; 'nomerge' manually added to ubsantraps.

Original file line number	Diff line number	Diff line change
`@@ -1,8 +1,8 @@`
`1`	`1`	`; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5`
`2`	`2`	`; RUN: llc -O3 -mtriple x86_64 -filetype asm -o - %s \| FileCheck %s`
`3`	`3`	`;`
`4`		`-; This test shows that ubsantrap can, in the absence of nomerge, be merged by`
`5`		`-; the backend into a single ud1 instruction (thus making debugging difficult).`
	`4`	`+; This tests that the nomerge attribute for ubsantrap works correctly i.e.,`
	`5`	`+; they are lowered to separate ud1 instructions.`
`6`	`6`	`;`
`7`	`7`	`; The LLVM IR was generated from clang/test/CodeGen/ubsan-trap-merge.c with`
`8`	`8`	`; 'nomerge' manually added to ubsantraps.`